My last column considered the effectiveness of on-chip capacitance for series-terminated applications (Reference 1). This column extends that discussion to cover end-terminated systems.
Figure 1 depicts a simple totem-pole I/O circuit driving a perfect, symmetrically split end termination. Begin your analysis assuming that optional capacitor C1 is not connected and that a sinking current flowing constantly through Switch B holds the line low.
At time t1, you open switch B, ceasing to sink current –(1/2)(VCC/Z0). At the same time, you close switch A, sourcing a new amount of current, +(1/2)(VCC/Z0). The total step change in current VCC/Z0 forces one full-sized rising edge down the structure. Later, opening A and closing B causes the opposite effect.
The sinking current traverses switch B and package inductance LG on its way to the pc-board ground. When you change the current through the inductor, it reacts, causing a voltage glitch on node G1 at time t1. A similar glitch appears at node V1 when you close switch A. Given the same voltage swing, rise time, and line impedance, the voltage glitches in Figure 1 for the symmetrically split end terminator have the same magnitude as those in an equivalent series-terminated architecture.
In this end-terminated case, applying an on-chip capacitance, C1, between nodes V1 and G1 has no effect on the circuit. The on-chip capacitor is ineffective because both voltages move coincident with the same magnitudes and directions, so no current ever flows through the capacitor.
Now, take away the bypass capacitor and double up the driver to create a differential pair, using the same style of end terminations. The differential architecture ensures that a low-switching event, such as t2, simultaneously accompanies each high-switching glitch at t1.
Provided that the rate of current onset through Switch A matches the rate of decrease of current in the high-side switch of its differential counterpart, the perturbations at V1 perfectly cancel. This scenario is difficult to guarantee, but it is possible to achieve significant cancellation. The same situation applies to the perturbations at G1, given similar conditions on the design of the low-side switches. You may conclude that, in a differential system with symmetrically split end terminations, well-balanced drivers render the on-chip capacitance, C1, unnecessary.
A couple of other cases merit attention. Currents that a chip consumes internally that do not traverse the I/O pins are "core currents." These core currents always produce glitches that move in opposite directions at V1 and G1. Core currents always respond well to an on-chip bypass capacitor tied between the V1 and G1 rails inside the core section of the chip.
End terminations that are asymmetrical, such as Gunning-transceiver logic (GTL), have different properties from symmetrical end terminations. For example, in Figure 1, a pulldown-only driver with a 50-Ω pullup generates a double-sized glitch on G1 but no glitch at all on V1, which explains why GTL architectures sometimes need more ground pins than power pins.