Cut back the ground plane in the vicinity of the SMA signal pin.
Consider the problem of adapting a straddle-mount SMA connector for a 10-Gbps digital application (Figure 1). The microwave guru who designed this SMA connector configured it to optimally launch into a gigantic microstrip measuring 0.060 in. wide and 0.032 in. above the nearest ground plane. Microwave circuits often incorporate such giant microstrips to curb skin-effect losses.
Your digital system probably uses much smaller microstrips, with a much tighter trace-to-plane spacing. If you solder the straddle-mount SMA directly onto a small microstrip, it won't work properly. A small microstrip requires a ground plane much closer to the signal trace than a large microstrip. With a tight signal-to-ground spacing, the parasitic capacitance between the SMA signal pin and your closely spaced ground plane will be too great, producing significant reflections. Assuming H=0.006 in. for your digital microstrip, the excess parasitic capacitance of a 0.060-in.2 SMA signal pad is 0.69 pF, creating reflection coefficients at 1 and 5 GHz of 0.096 and 0.43, respectively. These reflection coefficients are too big. To make the circuit work at high speeds, you must reduce the parasitic capacitance of the SMA signal pin.
To reduce the parasitic capacitance, cut back the ground plane in the vicinity of the SMA signal pin. Figure 1 cuts back the ground plane in a beautifully tapered CPW (coplaner-waveguide) pattern. The trace on layer one mimics the exponential taper of the cut in the ground plane. This tapered CPW converts the large geometry of the SMA footprint to the small geometry of a 0.010-in. microstrip trace, while maintaining a constant 50Ω impedance along its length. A tapered CPW defies analysis with 2-D quasistatic tools, because its cross section changes.
If your 2-D field solver computes ordinary CPW configurations, you can use it to design some appropriate trace and cut widths for various cross sections along the exponential taper, but don't expect those answers to be completely accurate. Your 2-D solver will improperly model the influence of the exponential taper on the impedance of the structure. Stretching the taper into a long, slowly evolving shape reduces the rate of change at any point, thus improving the accuracy of the 2-D solver. However, a long, gentle taper defeats your purpose—you need a short taper. To obtain a short taper you have to build a few topologies or simulate them with a 3-D solver and then adjust the design to correct its impedance.
A great example of a constant-impedance taper is the Eisenhart SMA connector (Figure 2 and Reference 1). This connector uses a long, tapered metal cone inside the body of the connector to form a constant-impedance transition from the 7-mm connector body diameter to a microstrip measuring 0.047 in. wide. The Eisenhart connector uses a linear taper approximately 1 in. long. At frequencies as great as 18 GHz, the connector provides a reflection coefficient no worse than 7
The relative dimensions in the digital straddle-mount SMA layout are similar to those in the Eisenhart connector, so you should be able to use a similar rate of taper. Even better, the exponential transition, which etching technology enables, should provide even better performance than Eisenhart's linear taper. These factors indicate that a 1-in. exponential transition from the 0.060-in. SMA signal pad to a 0.010-in. trace should provide startlingly good performance from dc to 10 GHz.
The values below were generated using the coupled-line feature of Hyperlynx. They should provide a good starting place for your design of a CPW taper. Remember that these values won't be perfect, depending on the rate of taper adapted in your circuit. You'll have to build the structure (or simulate it with a 3-D field solver) and then tweak the geometry to get the TDR response just right.
The table calculates the CPW impedances assuming the structure is made from a center trace of width w on layer one, overlaid on top of a pair of big, fat ground traces on layer two. Each ground trace is 200 mils wide. The spacing between the ground traces on layer two (the ground-plane cut width) is s. The primary ground plane on layer two lies 6-mil beneath the surface, as shown in Figure 3.
Figure 3—The table lists CPW impedance assuming a coupled-line configuration involving two ground traces, each 200-mil wide and grounded at both ends, and one signal trace on the top layer centered between the two grounds.
There is a second ground plane shown in Figure 3. The second plane is solid with no cut, lying 32 mils beneath the surface. The second ground helps reduce EMI from the taper structure, and is required for my 2-D quasi-static field simulator to do its job. All the ground features should be tied to each other and the to SMA ground lugs with copious quantities of vias.
The assumed dielectric constant of the board is 4.3. The traces are coated with a 0.5-mil conformal coating having a dielectric constant of 3.3.
|Trace width w (mils)||Cut width s (mils)|
 Gupta, KC, et al, Microstrip Lines and Slotlines, second edition, Artech House, Norwood, MA, 1996, ISBN 0-89006-766-X.