My last column showed how the capacitance of a receiver loads an end-termination resistor, preventing the termination from doing its job. I used an isolation resistor (Figure 1), to partially decouple the effects of receiver capacitance from the termination and obtained a modest benefit. For now, ignore components T1 and L1. Assume that the external 50-Ω end-terminating resistor connects directly to the terminating bias voltage, VT. The FPGA-circuit model includes a short length of BGA-substrate trace plus the 9-pF capacitance of the die. Isolation resistor R2 brings into play a fundamental trade-off. Make the value too small, and the receiver capacitance, CIN, loads down the termination, which results in massive reflections. Increasing the value of R2 reduces the reflections but at the cost of degrading the signal rise time.
This time, I want to force the apparent termination impedance to equal precisely 50 Ω, with minimum degradation of the received-signal rise time.
Using reciprocal impedances accomplishes this trick. In the context of a constant signal impedance, Z0, every impedance, A(f), has a reciprocal impedance defined as B(f)=Z02/A(f). For example, in a 50-Ω circuit, a 9-pF capacitor and a 22.5-nH inductor are reciprocal impedances.
Assuming that A and B are reciprocal, see if you can prove for yourself the truth of this relation:
In this equation, the symbol "||" implies a parallel connection. The proof involves only simple algebra.
The equation suggests that, if you have any impedance, Z0+A, you may stabilize that impedance by placing it in parallel with the special impedance, Z0+B, where B is the reciprocal of A. The impedance of the resulting parallel combination precisely equals Z0 at all frequencies.In Figure 1, the input signal strikes two parallel paths. The lower path comprises an impedance, Z0+A, where Z0 represents the 50Ω resistor, R2, and A represents the transmission line and capacitor circuit within the FPGA.
The upper branch presents impedance Z0+B, where Z0 represents the external 50Ω termination resistor and B is the combination of T1 and L1.
Here is where the magic happens. If T1 in the upper branch and the BGA trace in the lower branch both share the same characteristic impedance, Z0, both lines have the same delay, and L1=Z02CIN, then impedances A and B will always be reciprocal. At that point, you meet the requirements for the application of the equation, so your overall terminating impedance equals precisely 50 Ω at all frequencies.
Second-order parasitics associated with the inductor and vias in the design surely affect circuit performance, but, to first order, this beautifully compensated termination works perfectly.