If you are using some form of delay line to match clock delays at all points of usage within a pc board, here's a short list of the items you need to match:
- Trace length,
- Trace configuration (microstrip or stripline, to match the delay per inch),
- Trace width and impedance (to match high-frequency losses),
- Dielectric constant (variations affect delay),
- Trace loading (more capacitance slows the rising edge),
- Clock-receiver thresholds (higher thresholds switch later),
- Terminations, and
- Serpentine layout.
A tight design process calls out explicit tolerances on all of the above items. Simulations usually show the slowest results with the longest trace on the slowest layer with the narrowest line (most skin effect), the greatest dielectric constant, the greatest capacitive load, the highest receiver threshold (for a rising-edge clock), and the termination with the least overshoot. Conversely, the fastest results appear with the shortest trace on the fastest layer, with the widest line, the lowest dielectric constant, the least capacitive load, the lowest receiver threshold, and the most overshoot. The difference between the slowest and fastest results for your system is the clock distribution skew.
When selecting a serpentine layout for your system, you should avoid long, coupled switchbacks. The term "switchback" refers to the commonly used U-turn format, in which a trace goes out and then comes back parallel to the outbound path. If the outbound and returning traces pass too close to each other, crosstalk coupling between the two traces may distort the output.
For example, a 50-Ω microstrip layout with 8-mil traces and 8-mil spaces set 5 mils above a solid reference plane produces NEXT (near-end crosstalk) of approximately 6% If the round-trip delay of each switchback is comparable with or greater than the signal rise time, each switchback translates the NEXT into a 6% distortion of the received signal. Any simulator capable of computing coupled transmission lines can show you this effect.
If, on the other hand, your switchback delay is much less than the signal rise time, the NEXT distortion blends into the overall shape of the rising edge in a special way. The NEXT distortion for short switchbacks doesn't affect the shape of the rising edge, but it advances the time of arrival. That is, short, coupled switchbacks produce smaller delays than the total trace length would indicate. Long, coupled switchbacks distort the signals.
The percentage reduction in delay for a short, coupled switchback can be as great as double the NEXT coefficient. When you place multiple switchbacks together in a serpentine configuration, the net reduction in delay can be as great as four times the NEXT coefficient.
The boundary between short and long coupled switchbacks is fuzzy. When the round-trip delay of a heavily coupled switchback far exceeds one-third of the rise time, you get seriously distorted signals; when it's much less than one-third, you get advanced timing. A 1-nsec rise time, used on an FR-4 dielectric, thus limits the maximum useful coupled-switchback length to about 1 in. (2 in. round trip). A 100-psec rise time limits the maximum coupled-switchback length to about 0.1 in.
Figure 1—Serpentine Layout affects signal quality and delay.
Figure 1 illustrates some of the trade-offs in serpentine design. Assume that Figure 1a produces a standard amount of delay. To save space, try squashing the traces closer together (Figure 1b). If the reduction in delay due to NEXT coupling requires the use of more sections (as shown), the layout in Figure 1b may not actually save space at all. Rearranging the serpentine to make it shorter and fatter (Figure 1c) may distort the received signal if the delay of each section becomes too great (and if the structure is significantly coupled). The layout in Figure 1d stretches the serpentine to eliminate the coupling issue. The stretched layout neither suffers from delay reduction or distortion nor wipes out big blocks of space for vias on other layers.