To Tee or Not To Tee

(Originally published in EDN Magazine, February 22, 1998)
 

The following simulations were generated by HyperLynx software. The driver in each case is a simple 3.3-V CMOS model, with 10-ohm output impedances in both HI and LOW states, 6-nH package inductance (BGA) and a 1-ns rise/fall time (10-90%).

The net topology shown on this page cannot be terminated satisfactorily. What I mean is, you can’t obtain a crisp first incident wave, of full size, with no reflections, and still meet the demands of good circuit-design practice. You can satisfy any combination of three, but not all four, of the above requirements.

The basic problem with this topology is that all three branches are long compared to the length of a rising edge. In other words, the signal delay on each branch (about 1 ns) is comparable to the risetime (also 1 ns). Such a net, if left unteriminated, will display full transmission line characteristics, with lots of overshoot and ringing.

Base Case
All traces are 50-ohm configurations. Voltages shown are at the driver and receiver locations (both receivers are the same). Step response is shown on the left, and a 66-MHz clock waveform on the right.

A slower driver will improve the ratio of line delay to risetime. A 15-ns driver is slow enough to damp out the ringing and reflections, whether we terminate the line or not. Unfortunately, this approach gives up on the first criteria: a nice, crisp first incident wave.

Slow Driver
With 15-ns driver the step response overshoot and ringing problem goes away, but the response is so slow it won't work at 66 MHz.

Attenuation can help. For example, a combination of a 50-ohm series termination at A, plus 50-ohm end terminations at C and D will damp all reflection modes. Unfortunately, this approach shrinks the received signal to only 1/3 of normal size.

Using Attenuation
Now let's try a both-ends termination scheme. Add a source termination of 50-ohm at the driver, plus end-terminations of 50-ohms at each receiver. The signal quality looks excellent, but the signal amplitude is cut down to 1/3 of normal size. With specialized receivers, this architecture can work wonders. With ordinary single-ended logic receivers, the diminutive received signal is useless.

A partial termination can help calm, but not totally cure, the ringing behavior. With 100-ohm terminations placed at positions C and D the first incident wave looks perfect, but after a while the reflections trapped between the low-impedance driver at A and the mismatch at junction B will cause the received signal to overshoot, crest, and rattle about.

Partial Termination
A partial termination, even if it’s not the correct value, helps calm the reflections. In this example, the driver is directly connected to the line (no resistor). Each receiver has a 100-ohm split termination (200 ohms to ground and 200 ohms to Vcc). In this case we are using two 100-ohm terminations because we know the driver can’t drive two 50-ohm loads and still meet V_OH and V_OL.

If we are willing to use a sneaky trick, we can satisfy the first three conditions. The trick is to implement segment A-B as a 50-ohm line, while implementing segments B-C and B-D as 100-ohm lines (it takes really skinny microstrips to get this to work, but it’s possible). When the signal from A hits junction B, it sees two 100-ohm loads in parallel, which is a good match for the 50-ohm segment A-B. No reflections result. Two 100-ohm end-terminations, one at position C and another at position D, will now perfectly terminate the whole net.

A Sneaky Trick
The following sneaky trick can help, but it’s a documentation nightmare. Here we have adjusted the trace widths to make segment A-B a 50-ohm trace, while segments B-C and B-D are each 100-ohm traces. A 100-ohm terminator is applied to each of the receivers C and D, providing almost perfect termination.

The little blip 4 ns into the step response is caused by the parasitic capacitances of the receivers (set to 3-pF each for this simulation). If we convert the topology into a source-terminated configuration, and if the line lengths are identical, even this tiny effect goes away.

Is this a good practice? Depends on your company’s internal design procedures. Most companies do not have a good way to document, track, and enforce tricky high-speed design rules. For example, if you write a little thesis on your schematic about some high-speed design trick you’ve used it’s unlikely that the layout person will ever see it. It’s not their job to read your schematic. It’s their job to hook up the net list, with the part footprints in their database, and the standard design rules enforced in their shop at the time of layout. Even if you get it right the first time, when the Tee layout is revised, as part of a future product upgrade, if you’re not there, the design is likely to get screwed up.

If you throw the Tee overboard the situation improves. For example, splitting A into a pair of low-skew drivers, with an independent, point-to-point link to each load, removes the tricky constraints. This dual-driver topology is the kind of design that will work now, and in the future, when some kid who doesn’t know an ohm from a hole in the ground picks up your design and tries to figure out what you did.

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