Every pc-board trace has a limited bandwidth. As chips go faster and faster, you eventually run into this limitation. To deal with it, you need to understand how the length and width of a trace affect its bandwidth.
Let's first define the bandwidth of a pc-board trace and then show some examples. The plot in Figure 1 illustrates the frequency response of some typical digital pc-board traces. These plots assume perfect line terminations. I define the bandwidth, B, for each plot as the 2-dB point on each frequency-response curve.
The importance of the trace-bandwidth parameter is as follows: Any rising or falling edge faster than one-half divided by B is significantly distorted. Slower signals suffer distortion of only 1 dB or less.
If you know how bandwidth varies with trace geometry, you can predict how changes in your system layout or operating frequency affect trace performance. Here, nature profoundly helps us: The bandwidth for almost all practical transmission lines varies in a simple way. For pc-board traces, the bandwidth is proportional to the square of trace width, W, and inversely proportional to the square of trace length, L.
This simple model holds reasonably well for all transmission lines in which skin effect dominates operational characteristics. That mode of operation accounts for almost every digital application operating at bandwidths higher than 10 MHz. Dielectric losses also play a minor role in the bandwidth equation, but, because skin effect causes the bulk of pc-board-trace loss, the (W/L)2 model holds fairly well for pc-board applications. (Ed. note: In 1999, the year of this publication, few applications operated above 1 Gb/s. For those that did, dielectric losses played a significant role.)
From the model, you can predict that increasing the trace length by a factor of k decreases the bandwidth by a factor of k2. Horrible, isn't it? The penalty for doubling the line length is a reduction in bandwidth by a factor of four.
A similar effect happens with trace width. Shrinking the trace width (assuming that you also lower the trace height to maintain the same impedance) also reduces the bandwidth. The penalty for halving the line width is a reduction in bandwidth by a factor of four.
Fortunately for us designers of high-speed systems, the bandwidth of a typical pc-board trace is incredible. An FR-4 strip-line trace that is 6 mils wide and 12 in. long has a bandwidth of 1.5 GHz and a 10 to 90% rise time of about 250 psec. If 1.5 GHz is not enough for your application, here are three ideas for increasing your trace bandwidth:
- Use wider traces. While you make the trace wider, raise it farther away from the nearest solid plane. This move results in a geometry that has the same impedance as, but less resistance than, the original. The bandwidth varies directly with the square of trace width.
- Limit your trace lengths. Longer traces display more resistance, causing more attenuation and, therefore, lower bandwidth. The bandwidth varies inversely with the square of trace length. If you must go a long way, consider using repeaters.
- Use a higher impedance trace. Raising the trace farther above the nearest plane (without increasing its width) increases the trace impedance. The ratio of series resistance to trace impedance controls attenuation, so raising the impedance lowers attenuation, thus raising the bandwidth in direct proportion to the square of the change in impedance.
As technology advances, more options become available. You can look at recent LAN standards to get a glimpse of what may someday become commonplace in ordinary digital logic families. For example, fixed equalization (10BaseT), adaptive equalization (100BaseTX), and multilevel coding with digital adaptive filtering and near-end crosstalk cancellation (1000BaseT) are fast becoming mass-market realities. Many designs have not yet reached the point at which trace bandwidth becomes a serious limitation, but just you wait. When typical trace widths go down to 0.002 in. and clocks reach the gigahertz area, you'll be there.