Relative Bus Delay
No terminations required
No special transceivers needed
Example: PC-AT bus
- 4" long (1 ns)
- 8 MHz clock (125 ns)
- bus timing ratio 0.008
The crucial ratio is the bus delay divided by the clock period.
I've plotted that ratio above, indicating a typical range of operation for most bus designs,
ranging from a low of 0.01 to a high of about 100. Bus designs which have a low bus timing
ratio are relatively easy to design, at least in terms of their bus timing.
Buses with a big bus timing ratio are more difficult.
As you work your way up the scale, a hierarchy of techniques is employed to produce
designs of greater and greater sophistication, which can reach to the uppermost area of the chart.
Let's look at a few examples.
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