Relative Bus Delay--Slow Mode
Focus on controlling clock and data skew
Use controlled-impedance drivers to limit settling time
Example: PCI bus
- 4" long (1 ns)
- 64 MHz clock (16 ns)
- bus timing ratio 0.062
The PC-AT bus, also called the ISA (industry standard architecture) bus, is a fairly simple animal.
It rates a length/speed ratio of less than one percent.
As a consequence, the timing constraints on this bus are rather relaxed.
It's easy to get it to work, and most cards inter-operate (at the physical level, anyway).
You can build this bus from just about any old CMOS ASIC cell.
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