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Relative Bus Delay-Skew Mode
Good terminations required
Clock is sourced in same direction as data
Works well with burst-mode transfers
Example: RAMbus
- 10" long (3 ns)
- 800 MHz clock (1.2 ns)
- bus timing ratio 2.5
The next step up in performance occurs when the bus delay significant enough compared
to the clock period that we start thinking about optimizing the clock skew.
When you write out the equations for bus timing, the clock skew between cards has as
much to do with the cycle time as any other delay component. If we squeeze the clock
skew, we can usually improve timing.
And there's a big incentive to work on the clock skew (as opposed to trying to
improve the performance of any other element in the system). That's the fact that
there exists only one clock, compared to the many, many other data and control signals.
So, a lot of designers spend time optimizing the clock skew. This is probably a fairly
effective thing to do. There's a lot of help available for this, too, in the form
of low-skew clock generators and buffers.
Just working on clock skew gets you up into the territory of a 30 percent bus timing ratio.
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