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Relative Bus Delay-Distributed Clock Mode
A bus timing ratio near unity requires some very careful thought about the timing budget.
These systems often give up on the idea that everyone along the bus should be operating
in the same cycle at the same time.
Instead, they go with some form of a distributed clock, either
- Two clocks, one for each direction
- A separate clock sourced from each transmitter
The idea is to arrange to the clocking scheme so that each receiver gets a clock
right in the middle of its received data bit as that data bit passes along in front of it.
Obviously, all the receivers won't be getting data at precisely the same time.
Therefore, they all benefit from tiny adjustments in their timing.
A good example of this architecture is RAMBUS. They use the two-directional clock idea.
Note that there is often some overhead associated with switching clocks, so this is a
scheme that works best with burst-mode transfers, where you set up the clocks, let the
system fly for a while, and then reset the clocks again.
This system is in use at speeds of up to 800 MHz. As we go forward into the future, however,
at even higher speeds, the bus timing ratio will continue to grow. What happens in the extreme?
At the top end of the scale is the true distributed system architecture.
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