I have received an app note from a vendor of a multimedia signal processors. They are targeting a memory system with 4 sync DRAMs running at 125 MHz. Data wires will go to 2 DRAMs each, and address lines go to 4 DRAMs each.
Their app note suggests that address lines run in a "T" shape. The address line driver will be at the bottom of the "T", with two DRAMS on the left of the "T" and 2 on the right. They suggest that the address lines from the processor drive to the center of the "T", and that they be 50 Ohm on the outside layer over a ground plane.
Here is the odd new idea. They spec a ground plane cut under the DRAMs, so that the address bus in that part of the circuit sees it's return current on the ground plane at the far side of the board. (They don't stress the importance of VIAs to let the return current jump between ground planes.)
The near ground plane is 5 mills or so below the address bus. However, in the area of the ground plane cut, the nearest ground is 35 mills away, so the traces can be higher impedance. In fact, I think the idea is that the traces on the arms of the "T" be around 100 Ohm including load, so that two traces meeting at the center of the "T" make a parallel 50 ohm load.
So. The question. This seems very tricky, and suspicious. Is it clever, or is it troubling?
How does this idea compare to the simpler one of routing 2 wires away from each processor address pin, and having each wire drive 2 DRAM address inputs? This would increase the load on the driver, which would slow it down. How would the speed compare? Note that these are not the clock wire, so the signal can slop around for a while, if it gets stable in time.
Will the address traces crossing the ground plane cut radiate like crazy? Is this a good idea? Are there better ideas?
Thanks for your interest in High-Speed Digital Design.
I'm going to assume that we are talking about a single cut that spans several traces. In that case, the cut in the ground plane does three things:
- Adds a little lumped inductor in series with each trace;
- Couples together all traces that pass over the slot;
[NOTE--if there is a separate cut for each trace, then you still get (1) and (3), but not (2)].
In this design, the crosstalk (2) may not be a problem. After all, it's a synchronous bus, and it's very short. Perhaps you have time for the extra crosstalk to settle out.
The effect of (1), as you suspect, is to increase the effective impedance of the trace. That's probably a good general idea. The problem here is that we have done it in a rather uncontrolled fashion. Unless the vendor provide no rules for the power-ground spacing, location of other nearby planes, exact slot size and position, along with some idea of how to *test* a trace to see if it's correct, I would tend to steer away from this idea if I had any other alternatives.
Item (3), as you mentioned, might or might not be a problem depending on other factors at work in your system.
Let's talk for a second about the wisdom of using high-impedance traces in this application. I'll start with the observation that the DRAM loads significantly alter the transmission line characteristics. For example, the total capacitance of each net is pretty much fixed by the DRAM input capacitance, which is huge compared to the expected total capacitance of each PCB trace. Therefore, the only net parameter we can truly control is the total inductance of the net, L. As we increase L the effective loaded transmission line impedance (the net impedance) goes up proportional to the square root of L. That makes it easier to drive the net.
On the other hand, as we increase L the effective total delay of the transmission line also increases proportional to the square root of L. In other words, if we add too much L the net delay will grow too large. The correct amount of L is an amount just sufficient to permit your gates to drive a full-sized first incident wave, without unnecessarily increasing the overall delay.
Ways to Terminate This Net
If all segments are very short you don't need a termination (and you probably don't need my advice, either).
If the center leg of the "T", the one leading to the DRIVER, is sufficiently short (line delay less than 1/10 of the risetime), but the other two legs leading to the DRAM loads are long, then there are two correct ways to terminate this structure.
Way #1: End Termination
DRAM DRAM DRAM DRAM ET -----+--------+--------------+-----------+----ET long | long ST | DRIVER
Place a split termination at the far end of each long trace (positions ET). The apparent driving-point impedance of each split terminator should be sqrt(L/C), where L is the total net inductance of each long segment (natural trace inductance plus the lumped-L), and where C is the total net capacitance of each long segment (natural trace capacitance plus the lumped-C DRAM loads).
Way #2: Source Termination
Design the driver so that its source impedance (position ST in teh drawing) equals (1/2)*sqrt(L/C). This is the approached used in PCI bus.
Way #3: Tricky Termination
If all three legs are long the problem gets much harder. In that case, if you really need a full-sized first incident wave, then the only effective strategy is the one you mention, which attempts to make the impedance of each of the top "T" section equal to twice the impedance of the center leg. That works best if you keep the net symmetric around the main driver. If the net is totally symmetric, either of the two termination strategies outlined above could work... but, using high-impedance lines would be a tricky way to have to go.
Dr. Howard Johnson