Power Bus Noise
High-Speed Digital Design Online Newsletter: Vol. 1 Issue 09
Our most recent work has been focused on trying to understand the sources of power bus noise. The CMOS devices that we have looked at so far can draw peak currents of about an Amp from the power bus (when a single gate switches) if they are connected with a sufficiently low inductance. This appears to be a "crowbar effect" current, since the current drawn is independent of gate loading and the current goes in on the power pin and out on the ground pin. This current spike has a greater impact on the power bus noise than the current drawn from the power bus to generate the signal.
Have you encountered this in your work? We have not looked at enough devices to know whether this is typical for CMOS. However, if it is, it seems that the best decoupling scheme (from an EMI perspective) is to purposely introduce a little inductance between a CMOS chip's decoupling capacitor and the power bus planes (e.g. run the power leads from a chip to a local capacitor, then connect to the planes).
I am aware of two separate effects inside a CMOS chip that contribute to power consumption of this nature.
(1) When a gate's output stage switches from HI to LO the lower FET begins to conduct *before* the top FET is completely turned off. (Same thing happens going LO to HI). This has traditionally been only a small source of power dissipation. You can observe this effect in SSI circuitry by switching an inverter gate input slooowwwwlllllyyyyy, and watching the power supply current sweep out its characteristic current curve as the output switches. (see figure on p. 43 of my book).
(2) There are (sometimes large) parasitic capacitances to ground and Vcc associated with the output circuit. Each time the gate switches, currents must flow through the power and ground pins to charge up these pesky little capacitors. I think this is very likely the source of your observed current pulses. (see general discussion on p. 41 of my book). To properly represent all the effects in a real circuit, you will need to model a parasitic capacitance (C1) from output to the internal Vcc rail inside the chip, and another one (C2) from output to the internal ground substrate of the chip.
When switching HI, the current flowing in the Vcc pin as we charge the lower capacitance (C2) is (C * dv/dt). To get as much as 1 amp (Wow!) at a 1 ns switching speed, you would need 200 pF (assuming 5v logic). I have seen gates which exhibit in the Tri-state condition an output capacitance of as much as 50 pF, but not as much as 200 pF. Maybe there is something else going on here...
Regarding the technique you suggest for isolating these noisy gates from the power supply, I have always advised against adding any inductance in series with the power connections on a chip. In my opinion, any inductances in series with the power or ground connections will just exacerbate ground bounce problems due to output loading, which seems inadvisable.
My best advice is to design a power system with a sufficiently low driving-point inductance to limit the voltage spike generated by your noisy gates.
By the way, I'd be curious to know what kind of gate it is.
Dr. Howard Johnson