Dr. Johnson, I would like to make a few comments and relate some observations about the subject of BYPASS CAPACITOR LAYOUT in one of your online newsletters.
You recommended that instead of the chip pwr/gnd pins being routed first to the cap, then the cap being routed to the planes, the preferred way would be to route the IC pins to the planes, and the nearby bypass cap to the planes. I agree that this configuration would seem to minimize the inductance seen by the IC and therefore minimize ground/power bounce. However, let me relate an experience we had in which we decided not to do it that way.
We have a mixed signal chip: a chip with a noisy digital section powered by digital supply DVDD/DGND, and a sensitive analog section, powered by analog supply AVDD/AGND. The board on which the chip is mounted has one ground plane, to which both DGND and AGND are referred. As on an ADC, both grounds must be referred to one "system ground." The AVDD analog supply is bypassed to the ground plane close to the chip. Our question was: how to connect the digital supply wires and bypass cap??
What we found was that if we connected the DGND chip pin directly to the ground plane, and then connected the digital bypass cap to the ground plane, the digital-supply transients then all flowed in the ground plane. Since no ground plane is perfect, the ground plane currents caused small potential differences across the plane, and digital noise then coupled directly into the AVDD analog supply through the analog bypass cap, since that cap is connected to the ground plane. The amount of noise coupling wasn't huge, but it was enough to mess up the analog section. Then we decided to try another method, namely connecting the DGND/DVDD pins of the chip directly to the digital bypass cap, THEN referencing the cap ground pad to the ground plane. In this case, much of the digital transient current flows only in the loop containing the cap, and NOT in the ground plane! This resulted in a cleaner system ground reference. The difference in performance was quite striking.
It seems to me that by using this approach, you trade digital supply bounce for a cleaner system ground plane. If you can tolerate a little more bounce on your digital supply pins, wiring the bypass in this way keeps the current off the ground plane. This would seem to be a really important issue in mixed signal design. Any thoughts or comments on this?
Thanks for your interest in High-Speed Digital Design.
I'm glad to hear you found something that fixed your noise problem. While I am usually not one to argue with success, and I certainly don't want you to change anything that is working, I am compelled to point out that your assertion that you have prevented digital transient currents from flowing in the ground plane is not correct.
Your chip generates several different current flow patterns, only one of which you have conquered.
CMOS and Bipolar chips create large transient current flows in three situations: (1) current flows directly from Vcc to Ground (internal power absorption); (2) current flows from Vcc, through the chip, to the output pin (driving high, sourcing current to the loads); (3) current flows from the output pin, through the chip, to the ground pin (driving low, sinking current from the loads)
Your architecture (the single point ground idea) works only for current flow pattern (1), which, for most SSI and MSI chips, is by far the smallest of the three problems.
For situations (2) and (3), the chip is creating large transient current loops that involve its output pins, external loads, and the power and ground planes surrounding the chip. For example, suppose the chip is connected to a long 50-ohm trace, and further suppose that trace is routed on a layer adjacent to the ground plane. When the driver forces current into and out of that trace, an equal and opposite current flows on the ground plane, directly underneath the trace. This reaction current (or returning signal current) re-enters the driver through either the Vcc or Gnd pin, depending on whether the driver is switching high or low, respectively.
Your positioning of the chip, and the details of your new layout, certainly seems to have reduced the noise in the analog section of your logic, but more likely due to a fortuitous cancellation of noise effects rather than through any generally reliable physical phenomenon.
A more general-purpose method of preventing digital currents from circulating in the analog ground plane would be the following (this sort of layout is used with A/D converters in excess of 20 MHz with more than 8 bits):
- Draw a line across your board, dividing the analog and digital regions.
- Cut ALL plane layers along this line, partitioning the card into two regions. We call this structure a "moat" (with many thanks to Michael King for teaching me this layout trick).
- On the ground plane layer(s), use a 10-mil wide moat. On the power plane layer(s), use a 100-mil wide moat.
- Now tie together the analog ground and the digital ground at ONE and only ONE point. This will be the "drawbridge" that goes across the moat. The drawbridge is usually about the width of your A/D chip package.
- The A/D chip must straddle across the drawbridge.
- NO SIGNALS WHATSOEVER are permitted to cross the moat (to do so creates a "slot antenna" radiator which will hammer your card with crosstalk, and create huge amounts or EMI, totally defeating your purpose).
- Any signals that must pass between the analog and digital sections MUST pass across the drawbridge (not across the exposed moat), and must do so on a layer adjacent to the drawbridge.
- Special power filters are to provide a smooth, noise-free analog Vcc supply (linear regulators work best).
- Anchor the "ground" end of your analog-supply bypass capacitors on the analog side of the moat, and your digital-supply capacitors on the digital side of the moat.
This structure prevents high-speed transient currents in the digital region from wandering over to the analog region and doing damage. If you need more than 80-dB isolation between regions at frequencies of 100 MHz or more, the moat and drawbridge structure can do the job.
Now, here is the catch, and this is a BIG problem. We have divided the card into two ground regions, digital and analog. We have provided one connection between them (the drawbridge). We must now EXCLUDE all other inter-ground current pathways. NO OTHER CONNECTION must exist that would permit current to circulate between the digital ground and the analog ground. If there exists any other inter-ground connection besides the drawbridge, you will end up with currents circulating from digital ground, through the second inter-ground connection, to the analog ground, and back through analog ground to the drawbridge returning to the digital ground. Yuk.
It's not easy to get this setup to work properly. Approaches I've seen used include (a) tie the analog ground to the drawbridge only, and use optical, differential-balanced, or transformer coupling for all analog I/O, or (b) put a solid metal sheet under the cord, and ground the digital area, the drawbridge, and the analog area to it. Either approach tends to reduce the circulation of stray digital currents in the analog zone.
Dr. Howard Johnson