Public Seminar Schedule, taught by Dr. Howard Johnson

High-Speed Digital Design

 

Silicon Valley, CA
Huntsville, AL    

Coming Spring 2011
October 25-26, 2010

Adv. High-Speed Signal Propagation

 

Huntsville, AL    

October 27-28, 2010

High-Speed Noise and Grounding

 

Silicon Valley, CA    
 

Coming Spring 2011
 

 

 

Metastability in Flip-Flops

HIGH-SPEED DIGITAL DESIGN - online newsletter -
Vol. 3 Issue 15

*---------------------(QUESTION)---------------------*

METASTABILITY IN FLIP FLOPS

J. Villela writes:

In your book you talk about metastability in flip- flops, and you suggest that two flip-flops are a good way to avoid it. I'd like to know what happens if you have two flip-flops in series, both using the same clock, and the first one goes metastable. Does the second one clock out whatever the first one passes, even if it's junk? Or does it default to a LOW?

*----------------(DR. JOHNSON REPLIES)---------------*

Thanks for your interest in High-Speed Digital Design.

On a good flip-flop, when you meet the setup and hold window, it always gives you a solid output within the guaranteed maximum clk-Q delay.

The essence of metastability is this: when the data input violates the setup and hold window, if it transitions close enough to the exact sampling moment within that window, the flip-flop may take LONGER than the normal clk-Q delay to make up its mind. As the flip-flop is deciding what to do it may stay LOW, and then later pop HIGH (or vice- versa), or it may jump one way, and then come back. Some very old parts would oscillate for a while before settling down (I haven't seen that in twenty years).

The extra delay may be ten or twenty times longer than the normal clk-Q delay. This extra time is called the metastable resolution time.

OK, now let's treat your question. Suppose we label the two flip-flops A and B. When an input transition hits within the metastable sampling window of the A, it causes an inordinately long delay in the output of A.

When this delayed output arrives at B, everything is usually alright UNLESS the delayed signal transition from A happens to hit RIGHT ON TOP OF the metastable sampling window for B. In that case B produces a long clk-Q delay as well, which could incapacitate the succeeding logic.

As you might imagine the probability of this scenario happening is extraordinarily small. In a practical circuit, cascading two flip-flops practically squares the probability of failure. Adding the second flip-flop can easily turn a circuit that used to fail one time out of a billion (with only one sampling flip-flop) into a circuit that fails only one time out of a billion-billion (with two sampling flip flops). It's a very powerful technique.

Best Regards,
Dr. Howard Johnson


To Subscribe to this HSDD Newsletter, send an email to hsdd-request@freelists.org with 'subscribe' in the subject field.

All Publications by Dr. Howard Johnson except as noted.
Signal Integrity Training Classes taught exclusively by Dr. Howard Johnson - for full schedule, see www.sigcon.com
© 1999 Signal Consulting, Inc., Dr. Howard Johnson. All rights reserved. • site map