Interplane Capacitance

HIGH-SPEED DIGITAL DESIGN - online newsletter -
Vol. 3 Issue 21

*---------------------(QUESTION)---------------------*

INTERPLANE CAPACITANCE

Steve Ting writes:

In your High-Speed Digital Design On-Line Newsletters, there is one article, "High-Speed Return Signals," that discusses return paths.

I have a question on the area size selected when dealing with the current return through "natural interplane capacitance".

You mentioned "If you are working with edge rates of about 1 nanosecond (500 MHz), then it is reasonable to assume that at any particular time, a disk of capacitance with a radius of about 1" is working in your favor as a conduit of interplane current."

I cannot dig out why that inference should be assumed. Could you please give me some hint?

Thank you very much.

*----------------(DR. JOHNSON REPLIES)---------------*

Thanks for your interest in High-Speed Digital Design.

Consider this thought experiment: Imagine we have a chip connected to a pair of solid power and ground planes. Further imagine that this chip creates unacceptably large 1-ns glitches Vcc-to-ground voltage.

Now you attempt to improve the situation by connecting a lumped-element bypass capacitor to the power and ground planes. Make the connection from the planes to the capacitor using a pair of long wires (the capacitor just hangs off the side of the board on a pair of long wires). Assume that the round-trip transit time from the power planes to the capacitor and back is known.

I claim that if the round-trip transit time to the capacitor and back were as large as 1 ns, the capacitor would be totally ineffective. Any glitches present would have come and gone before the capacitor would have had any possibility of affecting the situation. I say the capacitor needs to be located within a round-trip transit delay of less than 1/3 of a risetime to significantly attenuate the power supply glitches. In addition to the round-trip timing requirement, the capacitor also needs to have a sufficiently low impedance at the frequencies of interest in order to be effective.

Let's now turn our attention to the case of a surface-mounted capacitor soldered to a pair of power and ground planes. To analyze this situation, first assume that noise is injected into the power and ground planes at a fixed location. Signals injected into the planes will propagate radially away from the point of injection, moving with a speed controlled by the properties of the dielectric material that separates the planes. If the dielectric material is FR-4, the speed of propagation for power-and-ground disturbances is roughly 6 inches per nanosecond.

If you locate a capacitor within a 1-inch radius of a noise-producing chip, the round-trip transit time from the noise injection point to the capacitor and back will be 1/3 ns or less. In a system with 1-ns risetimes, interplane capacitance within this one- inch disk is helpful, outside of that range it becomes very ineffective.

Best Regards,
Dr. Howard Johnson

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