What's That Plateau?
High-Speed Digital Design Online Newsletter: Vol. 7 Issue 03
Today I am on the way to England for an extraordinary week at the University of Oxford. I will be teaching two courses for the department of continuing education as part of "High-Speed Digital Engineering Week". This event brings together five of the world's best-known experts in signal integrity and noise issues for a week of seminars, panel discussions, and student interaction. The event is open to all professional engineers without regard to prior affiliation with the University.
This is the first time any major university has organized and delivered such a comprehensive palette of short-courses and activities for high-speed digital designers. It is exciting to be part of this effort.
I have been working with the University of Oxford for many years now towards the goal of establishing a permanent home in Europe for signal integrity research. This summer's program represents a big step along that path. I do not know where one could go for a better educational experience.
More details on this incredible program are available at: High-Speed Digital Engineering - Oxford University
What's That Plateau?
On a recent trip to Phoenix I faced a perplexing situation. The design group at a local company had hooked up a big CPU through its bi-directional memory interface to a memory subsystem. The interface length spanned roughly 3 inches from chip-to-chip.
When blasting out data bits, writing from the CPU into memory, the data-bit voltage waveforms recorded at the memory looked quite reasonable. The apparent risetime was 400 ps, as measured using a 6-GHz probe with 0.5-pf capacitance, touching the BGA ball of the memory chip, and with a very short ground connection.
When reading data bits the other way, reading into the CPU from memory, the data-bit voltage waveforms recorded at the CPU chip looked funny. Each rising edge came up roughly halfway and then stalled out, creating a flat plateau that lasted about 350 ps before completing the rise up to full value. The final, delayed edge of the waveform was not quite meeting the timing budget, yet the system worked beautifully.
The design engineers were understandably concerned about the plateau artifact. They regressed to several previous generations of designs and found that, with their new high-speed scope, they could see similar artifacts on almost every design that used that particular CPU. Writing data bits out from the CPU to memory always worked, but reading back in the waveforms suffered the "plateau". Did this mean all previous designs violated the timing budget?
Did I mention that the layout of this design was superb. Each data track was a differential pair with matched-length, controlled-impedance routing all the way from die-to-die, including the BGA routing inside the BGA package at each end. Each end, when transmitting, had a 100-ohm differential output impedance. When receiving, each end went into a tri-state (high-impedance) condition. There were the usual unavoidable glitches on the signal due to probe capacitance and BGA-pcb transitions, but nothing too problematic. The big issue was the plateau.
The engineers brought up several possible explanations, beginning with a series of questions about whether it might be a capacitive effect, specifically a non-linear capacitance, or perhaps some non-linear artifact of the differential input circuitry. This explanation seemed too much of a stretch to me. If an I/O circuit behaves that poorly, it is probably broken.
Perhaps could it be a ground-bounce or crosstalk effect? Crosstalk was ruled out because no glitch appeared unless the victim line was changing. The plateau was definitely self-induced.
As part of the ground-bounce discussion, I asked if they had any pictures taken from the driven end of the net. These pictures yielded a valuable clue, as you will see.
After eliminating several other possibilities through diagnostic questioning, I went to the board and drew out the waveforms for a simple, series-terminated configuration. As you may recall, the waveforms associated with this diagram work as follows:
- The source-terminated driver initially produces a half-sized edge.
- As measured at the source, the first edge remains half-sized for one round-trip time.
- After that, the signal at the source rises to its full and final value.
In essence, the source-terminated configuration produces a very long, very flat plateau (it's the only simple circuit that does that).
Working with the pictures taken at the memory-driven end of the net, we measured the length of the source-termination plateau. Given a 3-in. trace length, and a dielectric constant of 4.3, I expect to see a plateau length like this:
Round-trip-time = (2)*(85 ps/in.)*(sqrt(4.3))*(3 in.) = 1058 ps
What we measured from the pictures looked more like 1400 ps, considerably more than expected. That is a huge clue. It says that the actual line delay is considerably longer than one might predict based on looking at the layout. The additional delay implies that there must be an additional inch or so of trace hidden somewhere. It turned out that the extra inch of trace was hiding inside the CPU BGA package.
These engineers had made the mistake of thinking they were looking at the end of the transmission structure because their probe was set at the BGA ball of the CPU chip. In fact, the probe was located a substantial distance away from the end, where in this case the word "substantial" means a substantial distance compared to the rise/fall time of the signals. At a rise/fall time of 225 ps (the actual source rise/fall time in this case) a distance of 1 inch is definitely substantial.
On a series-terminated line, the waveform measured at the source end of the net displays a prominent (and familiar) plateau. As you slide your probe toward the end of the structure the two half-steps framing the beginning and end of the plateau slide progressively towards each other. When you get close to the end of the net, when the round-trip time to the end and back equals the rise time of your signal, the two half-steps begin to merge into a single full-sized step. At the bitter end you see only one full, complete step.
Any time your probe sits so far from end of the structure that the round-trip delay to the end and back exceeds the signal rise/fall time, then you will see the plateau. That is all that was happening in this case. The plateau appeared because the probe was not actually at the end of the structure.
Einstein said that some of the worst mistakes we can make happen when we confuse a symbol for a thing with the reality of the thing itself. In this case, the designers confused the BGA ball as a symbol meaning "end of transmission line" with the actual end of the transmission line structure buried deep within the chip.
The source-termination framework also clears up another artifact. The waveform when writing data to the memory end of the link had always displayed a slower-than expected rise/fall time. In light of the newly discovered internal delay issue we found that 1/2-in. of additional trace internal to the memory, while not enough to produce a fully-visible plateau, was certainly enough to degrade the risetime of the resulting signal at that point from 225 ps (the true value) to 400 ps (the observed value at the BGA ball of the memory package).
Fortunately for this design group the plateau did not require any remedial action; the system itself was fine. That is one of the few times in life I have been able to fix a problem by doing nothing—I merely pointed out that the problem wasn't really a problem.
What the client did next was to undertake a complete re-thinking of their simulation process. In the future, they will simulate not just the signal at the endpoints of a link, but the signal at the probing positions, so they can tell what the signal is supposed to look like at those positions.
In the future, whenever you see an unexpected plateau, you may immediately suspect the presence of some unaccounted-for transmission line stub.
Dr. Howard Johnson