Alphabetical Index
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- All Publications © by Dr. Howard Johnson 1993 - 2012 except as noted.
- View the publication list by keyword or in chronological order.
10 Reasons Why I Love the BGA chip packaging -- Ball Grid Array (BGA) packages are taking the industry by storm, and I’m glad to see it. ED 3/17/1997
2-D Quasistatic Field Solver simulation, TEM mode -- If your system violates any of these assumptions, the simulator produces wrong answers. EDN 9/27/2001
A Time for All Things chip packaging, differential signaling, ground bounce -- There is a good time and a bad time for a chip to sample its digital inputs. EDN 6/21/2001
A transmission line is always a transmission line characteristic impedance, reflections, transmission line -- Does the input impedance behave one way on a long transmission line but differently when the load is adjacent to the driver? How does it know what to do? EDN 4/4/2002
AC Coupling Layout (for XAUI 3.125 Gb/s) data coding, layout, reflections -- The parasitic body capacitance of the AC coupling caps perturbs the characteristic impedance of your transmission line. Newsletter v10_02 5/18/2007
AC Terminators power dissipation, termination -- The promise of an AC terminator is the idea that maybe, just maybe, there is a value of C big enough to make a good termination, but at the same time small enough to not draw much current from the source. Newsletter v2-24 9/9/1998
Acceptable Crosstalk crosstalk -- What is the limit of crosstalk that can be ignored? (and frozen turkeys) Newsletter v5- 11 10/30/2002
Acceptable Failure metastability -- Without clearly quantified limits on the "acceptable probability of failure," you never know whether you have implemented too little or too much of your favorite failure- rate cure. EDN 3/2/2000
Accurate Series Termination termination -- How are you supposed to calculate an appropriate series termination when you have such a large variance in the source impedance of the driver? Newsletter v4-14 11/1/2001
ADC grounding grounding -- Chip designers often internally partition the ground-reference net (or substrate) for an ADC into isolated analog and digital regions. EDN 12/7/2000
Adequate Bandwidth bandwidth, probes, testing -- A bandwidth-limit feature performs a service somewhat like vertical averaging, in that it reduces random noise, but it does not require a repetitive signal. Newsletter v11_03 5/19/2008
All About Surface-Mount Ferrites EMC, ferrite bead -- (by Lee Hill) Don’t use a ferrite bead unless you have data showing impedance versus frequency while under the influence of DC bias current, and don’t operate ferrite beads close to their maximum rated current. EDN 8/21/2008
Analog to Digital Conversion Parameters sampled data, testing -- Definitions of A/D specification terms, with hints about "specsmanship" in these numbers Newsletter v9_03 2/22/2006
Another Version of a Coax Probe probes -- What kind of probes do I need for looking at noise (<100 mV to 300 mV range) on the various ground pins of some gigabit transceivers? Newsletter v1-18 11/26/1997
Approaching the Edge management, probes -- Worst-case budgets don’t work if you don’t include all the necessary factors, or if you make wrong assumptions to fill in gaps in the available data. DesignCon 2004 2/1/2004
Ask For It rise time -- A limitation on the minimum rise and fall times is absolutely critical to proper functioning of digital hardware. EDN 7/6/2000
Asymmetric Noise Margins ground bounce, level translation, rise time -- Extreme asymmetries in the noise margin budget for a logic family create a preferred logic level. EDN 3/15/2001
Asymmetry in Broadside Configuration differential signaling, layer stack, layout, skew -- In general I avoid broadside-coupled traces unless they are made necessary by routing considerations. EDN 11/14/2002
Aunt Judy management -- Old Aunt Judy approaches you at a reception, with a little halt in her voice, and says, "You know about electronics, right? Well, I’ve got this old 8-track tape player… EDN 11/8/2007
Backplane Design back plane, differential signaling, layer stack, serial link -- Differential trace geometry, power and ground stackup for big backplane. EDN 5/25/2000
Benefits of Resistive Probe probes -- Here are ten good reasons to consider using a resistive-input probe. Newsletter v5-4 3/11/2002
BGA Crosstalk crosstalk, ground bounce -- Details, measured lab results, and theory of crosstalk involving hundreds of outputs switching simultaneously in a high-speed Xilinx Virtex-4 FPGA package, as delivered to the Xilinx tech on-line forum March 1, 2005. Newsletter v8_03 3/1/2005
Bi-directional Alternatives multi drop, PCI -- Hanging four loads on a bi-directional line; how PCI "reflected wave switching" works Newsletter v3-3 1/22/1999
Bi-directional Terminations multi drop, termination -- Using a series terminator at both ends of the line. Newsletter v2-20 8/6/1998
Big Buffer crosstalk, ground bounce -- Do you suppose there is much SSO noise margin left in a typical IC package design? Can you safely exceed the loading guidelines without causing SSO errors? I doubt it. Newsletter v8_07 10/18/2005
Big Hurl management, power system, transmission line -- Engineers enjoy a long tradition of experience with dynamic processes. We have developed over the centuries many diverse means of dealing with them. EDN 7/21/2005
Both-ends Termination termination -- The both-ends termination is supremely tolerant of imperfections within the transmission system and within the terminators themselves. EDN 1/18/2001
Breaking Up a Pair layout, reflections, stripline -- The two traces comprising a differential pair, when routed close together, share a certain amount of cross-coupling. This coupling lowers the differential impedance between the traces. EDN 11/9/2000
Building a Signal Integrity Department management -- What sort of a mission do you give to a department of signal integrity? EDN 6/4/1998
Bus Architecture and Timing back plane, multi drop, ringing -- The ratio (bus delay)/(clock period) is a key indicator of bus design difficulty. DesignCon 1999 1/30/1999
Buying Time differential signaling, skew -- Two strategies for minimizing the intra-pair skew accumulated by a differential net: (1) A pair that starts and ends going north has by definition equal numbers of right and left- hand turns. (2) How your layout enters or leaves a BGA makes a difference. EDN 5/2/2002
Bypass Capacitor Array bypass capacitors, power system -- This spreadsheet produces a beautiful color version of my figure 8.9 showing the impedance of each element of a power system and also the composite impedance of all four elements taken in parallel. Newsletter v6-02 1/24/2003
Bypass Arrays bypass capacitors, layout -- Does anyone out there actually DESIGN their bypassing networks? Newsletter v1-6 7/25/1997
Bypass Capacitor Layout bypass capacitors, layout, power system -- The primary symptoms of an inadequate, old- fashioned bypass capacitor array are increased power supply noise, increased crosstalk among signal traces, and increased electro-magnetic radiation. PCD 8/1/1997
Bypass Capacitor Layout bypass capacitors, layout -- Little traces between your bypass capacitors and the power planes have a big effect on performance. Newsletter v2-3 1/23/1998
Bypass Capacitor Sequencing bypass capacitors, layout -- A trace of any practical length placed in series with the power terminal of a high-speed IC (especially one with multiple VCC pins) radically increases power supply noise at the VCC terminal and should be avoided like the plague. Newsletter 9_07 10/4/2006
Bypass Multi-Valued Arrays bypass capacitors, power system -- I discourage engineers from combining together different- valued capacitors if they share the same package format. Newsletter v1-17 11/14/1997
Cable Shield Grounding cables, connectors, EMC, grounding -- Joe, I am going to disagree with your suggestion that a shield with a resistor at one end acts as an effective EMI shield. In high-speed digital applications, it doesn’t. Newsletter v2-2 1/16/1998
Capacitor Layout Matters bypass capacitors, layout, power system -- Your problem is likely caused by the layout, which has more than tripled the inductance of each bypass capacitor, not the values of types of capacitance. EDN 9/5/2002
Capacitor Placement bypass capacitors, layout -- The function of a bypass capacitor is this: to help returning signal current get from the board back into the driver. Newsletter v2-1 1/7/1998
Carrier Detection attenuation, serial link -- What happens when the opposing end of a link is disconnected, powered down, or disabled. EDN 9/4/2003
Characteristic impedance of lossy line characteristic impedance, dielectric loss, skin effect -- Skin-effect losses increase the real part of the impedance curve in the vicinity of the skin-effect onset, while the dielectric losses decrease the real part of impedance in the same area. EDN 10/3/2002
Charge Arrested EE basics, transmission line -- Animations showing the behavior of moving charged particles at an open-circuited transmission-line endpoint. Newsletter v14_03 4/21/2011
Charge in Motion EE basics, transmission line -- The slight compressibility of the sea of electrons in a metallic conductor generates most high-speed digital design effects. Newsletter v14_02 4/3/2011
Charge Unleashed EE basics, transmission line -- Charge carriers within a metallic conductor move under the influence of local electrical fields. Lacking any impetus to move; they remain still. Newsletter v14_04 8/10/2011
Chip Scale Transmission Lines ringing, termination, transmission line -- On-chip interconnections rarely require termination, but pcb traces often do. This conclusion is directly related to the properties of RC and LC transmission lines. Newsletter v7_01 1/29/2004
Clean Power power system -- With electromagnetic noise present, you can talk sensibly about potential differences only between points that are co-located, that is, points so close that the total field strength between those points is negligible. EDN 8/3/2000
Clock Jitter Propagation clocks, jitter -- Any sort of resonance, even a tiny one, spells disaster for a highly cascaded system. EDN 2/6/2003
Common Mode Analysis of Skew differential signaling, EMC, skew -- A twenty-percent skew creates a ten-percent common-mode component. EDN 1/22/2004
Common-mode ground currents grounding -- Instead of thinking of your digital ground region as a solid sheet, think of it as a picture frame. This simple model explains the basis of single-point grounding and many other common- mode noise issues. Newsletter v7_02 3/24/2004
Comparing Transmission Media attenuation, transmission line -- Transmission line comparisons may be complicated by various geometrical factors, but if you just remember that BIGGER conductors have LESS resistive loss you will have gone a long way towards understanding transmission line losses. Newsletter v12_05 7/26/2009
Confirm the Diagnosis connectors, probes, testing -- The confirmation step is crucial because it takes a lot of time to do re-work, or re-layout, and you must be sure of your conclusions (3.125 Gb/s serial link). Newsletter v11_02 3/26/2008
Connecting Layers connectors, crosstalk, layer stack, via -- In a multi-layer pcb the vias perform the role of a tiny connector, where the signal-to-ground-via ratio controls via crosstalk. EDN 7/22/2004
Constant-Resistance Termination reflections, termination -- The constant-resistance circuit forms an almost ideal termination regardless of the input capacitance of the receiver. EDN 6/12/2003
Constant-Resistance Equalizer equalizer, reflections, termination -- This circuit combines a good termination with a useful equalizing function. EDN 7/10/2003
Crossing the River reference plane, return current, rise time -- (by Doug Smith) Cross a river without a bridge and your clothes get soaked. Cross a split-plane gap with a high-speed signal and your whole development schedule gets soaked. EDN 7/24/2008
Crosstalk - Differential Vias crosstalk, via -- My CAD tools predict the level of crosstalk from differential digital traces to differential analog traces. That’s fine, but how about the crosstalk from differential digital vias to differential analog vias? How does that work and how big is it? Newsletter v8_02 2/15/2005
Crosstalk - Differential Vias with Grounds crosstalk, via -- Ground vias, used in conjunction with a differential pair, arrest the spread of crosstalk. EDN 4/28/2005
Crosstalk - Via to Trace crosstalk, via -- Measurements of crosstalk between an interplane via and an inner-layer trace relevant to the question of minimum separation between a sensitive differential analog pair and a digital via on the same PCB. Newsletter v8_01 1/25/2005
Crosstalk and SSO Noise crosstalk, ground bounce -- What you need is a simple experiment that will separate the effects of SSN (simultaneous switching noise) from other crosstalk. Newsletter v3-9 3/30/1999
Crosstalk at Right Angles crosstalk, layout -- Crosstalk for traces crossing at right angles. Newsletter v3-6 2/26/1999
Current-Source Driver back plane, transmission line -- A current-source driver overlaps its own signal on top of other signals passing by without inhibiting their progress. Newsletter v12_04 4/15/2009
(The) Curse of FAST Logic power dissipation, rise time -- Your circuits fill a motherboard, not a whole room, but still fall prey to the same signal propagation difficulties encountered in 1946 by Mauchly and Eckert on the ENIAC project. ED 5/1/1996
Dangerous Games management -- You were the kid popping wheelies, probing the limits of unstable equilibrium. On the playground swing set, every jump tested your knowledge of gravity, the nature of inelastic collisions, and bruised ankles. EDN 4/9/2009
Data Coding for Low Noise data coding, ground bounce -- Limited-weight codes provide noise-canceling properties similar to differential signaling, but using fewer interconnections. EDN 6/24/2004
DC Blocking Capacitor Placement data coding, level translation, reflections, serial link -- Slower systems sometimes benefit from placing the DC blocking capacitors close to the source, but not multi-gigabit systems. Newsletter v7_08 12/12/2004
DC Blocking Capacitor Value data coding, level translation, reflections, serial link -- How do I choose the value for a DC blocking capacitor in a serial link application? Newsletter v7_09 1/10/2005
DC Loading probes, testing -- This the first case I can recall of a transceiver whose output gets bigger when loaded. Not all LVDS outputs do this. Newsletter v11_04 7/18/2008
Debugging Hardware testing -- Debugging new hardware can be difficult and trying. The most common mistakes that most new engineers make when first debugging a system are: trying to debug too much at once, not testing their assumptions, and keeping inadequate records. EDN 8/16/2001
De-constructing Gain and Impedance from S11 attenuation, testing -- From measurements of S11, determine both the gain and characteristic impedance of a uniform transmission structure. EDN 11/10/2005
Delay Through Via delay, via -- For vias which traverse several planes, the delay is a function not only of the via but also of the position and configuration of nearby bypass capacitors. Newsletter v2-29 10/29/1998
Designing a Split Termination termination -- A Thevenin equivalent circuit helps you understand the need for two resistor values and how they work together to meet the impedance and current-drive constraints imposed by your driver. EDN 4/3/2008
Diagnostic Testing (and Tasting) management, testing -- Diagnostic testing requires a keen awareness of all aspects of the system at hand. The operator must remain ever vigilant during testing, aware of even the tiniest clue about system behavior. EDN 4/26/2007
Dielectric Loss Tangents attenuation, dielectric loss -- For a capacitor formed from a lossy dielectric material, the loss tangent is the ratio at any particular frequency between the real and imaginary parts of the impedance of the capacitor. Newsletter v4-5 6/11/2001
Differential (Microstrip) Trace Impedance characteristic impedance, differential signaling -- Many different combinations of height, width and spacing can generate the same differential impedance. Newsletter v5-2 1/22/2002
Differential Clocks clocks, differential signaling -- What’s the impact of using differential clocks in a parallel bus? Newsletter v1-10 9/4/1997
Differential Coupling differential signaling, transmission line -- Differential links need not be tightly coupled to work effectively. EDN 11/13/2008
Differential Crosstalk crosstalk, differential signaling -- I have a number of high-speed differential PECL signals that I need to route in parallel on the PCB. Newsletter v3-20 8/23/1999
Differential Pair Skew differential signaling, skew -- What impact does pair skew have on a received differential signal? Newsletter v1-7 8/5/1997
Differential Receivers Tolerate High-Frequency Losses attenuation, differential signaling, dispersion, serial link -- Differential receivers have more accurate switching thresholds than ordinary single-ended logic. EDN 11/28/2002
Differential Reflections differential signaling, reflections, transmission line -- Does the standard formula for reflections also apply to differential/balanced lines where two lines carry one signal? Newsletter v2-21 8/17/1998
Differential Routing differential signaling, layout -- Is it better to route differential traces over/under (broadside) or side-by-side (edge-coupled)? Newsletter v2-30 11/11/1998
Differential Signaling (Through Connectors) differential signaling -- I have 16 differential line pairs that have to go through a connector. What signal to ground ratio and pattern should I use? Newsletter v3-12 5/7/1999
Differential TDR differential signaling, probes, testing -- A differential TDR instrument provides two outputs, x and –x, which you connect to the traces under test. EDN 8/22/2002
Differential Termination differential signaling, termination -- Terrible things can happen to the common-mode artifacts if your trace delay equals one-quarter of the clock period. EDN 6/8/2000
Differential-to-common-mode conversion differential signaling, EMC -- Any imbalanced circuit element within an otherwise well- balanced transmission channel creates a region of partial coupling between the differential and common modes of transmission at that point. EDN 10/17/2002
Differential Transitions characteristic impedance, differential signaling, reflections -- The trick of inserting nearby compensation to fix problems elsewhere within the transition region is the secret to successful transition design. EDN 1/8/2009
Differential U-Turn connectors, differential signaling, stripline -- What is the effect of a split in a solid plane on the impedance of a coplanar differential pair? EDN 9/1/2000
Diode Terminations power dissipation, termination, transmission line -- Is there any technical basis for concluding that diodes provide a "cleaner" signal? Newsletter v2-19 7/28/1998
Directionality of Crosstalk crosstalk, layout -- (Originally titled: The Real Truth About Crosstalk) If you are trying to manage crosstalk from first principles, so it comes out right on the first spin, look into the new crosstalk prediction tools that feature IBIS I/O modeling. ED 8/18/1997
Double-Tracking back plane, crosstalk -- Let’s begin this discussion looking at the belt-and-suspenders, super-safe differential stripline architecture. Newsletter v7_05 9/7/2004
Driving the World of Gigabit Ethernet Gigabit Ethernet -- How should we best specify the I/O performance of drivers for the Gigabit Ethernet parallel interface? EDN 11/6/1997
Driving Two Loads layout, multi drop, ringing -- Any time you build a split-tee, always simulate the circuit with a maximal degree of capacitive imbalance in the receivers. EDN 7/19/2001
Driving-Point Impedance reflections, termination -- In a perfect series-terminated architecture, you can measure the driving point impedance at the driver, in the middle of the line, or a hundred miles away, the measurement always returns the same number: Z0. EDN 5/14/2009
Dual Ground Shields layer stack, reference plane -- Theoretically, if the planes are completely solid (no holes), they would act as near-perfect isolation boundaries, BUT you have to consider the holes… Newsletter v3-19 8/12/1999
Dual Transceivers layout, multi drop, rise time -- You can make extremely small, zero-cost, high-performance switches from ordinary solder pads and solder paste. EDN 6/10/1999
Earth Ground grounding -- The most important point to make with regard to grounding is that the input to every digital logic gate is a DIFFERENTIAL amplifier. Newsletter v2-12 5/7/1998
ECL and PECL level translation -- Can I directly connect a differential ECL signal to a differential PECL device? Newsletter v2-22 8/25/1998
ECL and PECL Reader Responses level translation -- Further discussion of ECL-to-PECL level translation. Newsletter v2-23 9/1/1998
EM Simulation Software EM fields, EMC, simulation -- (by Bruce Archambeault) Dr. Bruce Archambeault, distinguished engineer at IBM, IEEE fellow, and the author of the "EMI/EMC Computational Modeling Handbook", responds to my questions about electromagnetic (EM) simulation software. EDN 6/26/2008
EMI Simulations Tools EMC, simulation -- (Originally titled: EMI Simulation Tools) Many EMI simulators are embellished with flashy demonstrations, which, like the smell of coffee brewing, or the sound of bacon frying, promise more than they can possibly deliver. EDN 3/2/1998
Endpoint Distortion reflections, termination -- The nature of instantaneous signal distortion at the receiver is defined by an equivalent circuit comprising two components: a series resistance and a shunt capacitance. EDN 6/11/2009
Equalizing Cables cables, equalizer -- How do you equalize LVDS signals transmitted through cables of say 10 to 50m? EDN 8/2/2001
Equivalent Circuit Source Impedance high-speed digital design formulas -- What is the true source impedance of the equivalent circuit at figure 1.6 (page 13)? Newsletter v2-9 3/23/1998
Ernie's Story Ernie, management -- Engineers without a basic understanding of high-speed effects will likely end up just like Ernie, sitting in somebody else’s office, fidgeting and sweating. ED 12/1/1996
Erroneous Harmonics bandwidth -- You won’t find a quote in my book about "harmonics" because that isn’t a good way to look at the problem. Newsletter v4-9 10/4/2001
ESR of Regulator Output Capacitor bypass capacitors, management, power system -- How can the ESR of a bulk capacitor (tantalum or electrolytic capacitor) affect a linear voltage regulator? Newsletter v5-3 2/25/2002
Essential System Margin attenuation, management, serial link -- You should make tiny artificially adjustments to every line in the budget until you drive the system margin to zero. Only you will know where these adjustments are hidden. EDN 12/11/2003
Extra Fries, Please skew -- In the high-speed world, timing is everything, so I predict that delay-compensated clock repeaters will be really hot. EDN 1/7/1999
Eye Don't Like It jitter, simulation, testing -- An eye diagram makes a wonderful way to check finished system margins, but a terrible diagnostic tool. EDN 11/9/2006
Eye of the Probe probes, simulation -- If your probe loads the circuit and corrupts the physical measurement, how can you ever discern the "real signal" at C3 with no probe attached? EDN 12/1/2006
Ferrite Beads ferrite bead -- Ferrite beads come in two flavors: high-Q, resonant beads and low-Q, non- resonant beads, also called lossy, or absorptive beads. EDN 10/12/2000
Fiber-Optic Encoding data coding, Gigabit Ethernet -- Codes that scramble the data post-coding cannot control either the DC balance or the maximum run-length of the scrambled output. EDN 1/10/2002
Field Cancellation EM fields, microstrip -- Eddy currents flowing in a solid reference plane underneath a pcb trace partially cancel the magnetic fields emanating from that trace. EDN 3/3/2011
Finger the Culprit delay, testing -- When debugging a rare mode of failure, never attempt a direct fix. The test cycles associated with each attempted improvement will kill your development schedule. Your first order of business is to make the problem worse. EDN 6/21/2007
Flip-Flops metastability -- What actually causes the metastability in Flip- Flops? Newsletter v4-2 5/12/2000
(For Your) Protection electromigration, ESD, overshoot, ringing -- Protection diodes have a limited lifetime—don’t wear them out. EDN 12/9/2004
Four-Way Distribution layout, multi drop -- How to best distribute a bus to four different loads. Newsletter v1-14 10/17/1997
Frequent Obsession back plane, bandwidth, testing -- Frequency-domain instruments can play an important role in the measurement process, but should not be the main focus of your specification. EDN 10/12/2006
Front-Connected Power Supply EMC, grounding, power system -- Why connections on the front side of a plug-in card are a bad idea. Newsletter v4-17 12/5/2001
Fundametals of PCB Design layout, power dissipation -- This introductory overview of printed-circuit design treats the main difficulties you will likely meet when planning, designing, and manufacturing printed circuit boards for digital applications. Web 8/16/2010
(The) Future of On-Chip Interconnections interconnections, multi level -- Today’s chip-layout software takes into account the RC propagation delays of major bus structures and clock lines. In tomorrow’s designs, at even higher speeds, the full RLC nature of the on-chip transmission channels will emerge. EDN 2/3/2000
Gigabit Ethernet Gigabit Ethernet -- Gigabit Ethernet is going to be faster, with more parallel signals, and tighter layout constraints. PCD 2/1/1997
Gigabit Ethernet Specification Gigabit Ethernet -- The GMII is designed as a chip-to-chip interface. The expected link distance is therefore about 3 to 12 inches. Newsletter v2-6 2/2/1998
Going Non-linear simulation -- Spice is grand for non-linear circuits, but if your circuit is linear you might question whether it is best. The FFT shines as an efficient computational tool for long transmission channels. EDN 5/16/2002
Going Vertical EMC -- Keeping your traces close to a solid, uninterrupted reference plane is one of simplest, most effective things you can do to reduce electromagnetic radiation and harden your product against ESD. EDN 10/14/1999
Ground Bounce Calculations high-speed design formulas -- On page 62 of the High-Speed Digital Design Text… where does the factor of 1.52 come from? Newsletter v1-12 9/26/1997
Ground Current layer stack, return current -- Details the exact path of returning signal current when a chip switches HI or LO Newsletter v3-7 3/15/1999
Ground Fill EMC, grounding, reference plane -- Isolated, discontinuous regions of ground fill do not help reduce magnetic-field coupling between traces or radiation from the board. EDN 5/26/2005
Ground Fills EMC, grounding, reference plane -- The "poured ground" (more commonly called a "ground fill") is a technique useful on two-layer boards for reducing crosstalk due to ELECTRIC FIELD coupling. Superceded by "Ground Fill", EDN 26 May 2005. Newsletter v1-3 6/24/1997
Ground/Power Planes grounding, layer stack, power system -- At very high speeds, bypass capacitance needs to be within less than 1/10 of a rising-edge-length in order to function effectively. Newsletter v1-8 8/15/1997
Hairball Nets layout, multi drop, termination -- Terminating big globs of unstructured loads. Newsletter v4-10 10/8/2001
Half Measures power dissipation, reflections, termination -- (Regarding series termination) a good energy- balance equation often easily sums up the operation of a complicated system without bogging you down in details. EDN 1/5/2006
Healthy Power Ernie, power system -- When your prototype board comes back from fabrication, take the time to check the health of its power system. EDN 3/30/2000
Hidden Schematic EMC, grounding -- (by Bruce Archambeault) Dr. Bruce Archambeault, creator of the IBM EMC rule-checking program "EMSAT", says "Ground is a good place to grow potatoes and carrots", but a poor concept for high-frequency engineering. EDN 5/25/2006
High-Speed Backplane Connectors back plane, connectors, crosstalk -- Discusses the main factors affecting backplane connector performance, and predicts the future of backplane connector development. EMC Soc 8/17/2011
High-Speed Digital Design: Overview EE basics, management -- This survey article highlights key similarities, and important differences, between high-speed digital and microwave hardware, addressing factors related to transmitters, transmission pathways, receivers, and the people who design them. MTT-9 8/15/2011
High-Speed Return Signals layer stack, return current -- How do high speed return signals travel on a 4 layer pc board? Newsletter v1-15 10/27/1997
Holding On reflections, termination -- The tri-state feature, if available in your driver, acts as a sort of additional short-time dynamic memory element that you can use to extend the hold time of your driver. EDN 7/9/2009
Hot Plugging and Beefy Guys Named Mark hot plugging, power system -- Mark McGwire reminds me of some of the technicians I have seen working on large systems EDN 11/5/1998
How Close is Close Enough? layout, termination -- How close to the driver must you keep your series terminations? EDN 4/9/1998
How Fast is Fast? ringing -- In digital systems, the frequencies of interest depend on the edge transition time of the logic involved. EDN 7/2/1998
How Many Segments rise time, sampled data, simulation -- Examples show effect of inadequate number of segments in piece-wise linear (PWL) approximation. Newsletter v12_07 12/9/2009
I Still Love the BGA chip packaging -- Hate mail, mostly from mechanical designers and production test engineers, about BGA’s Newsletter v2-10 4/6/1998
IBIS simulation -- IBIS is going to solve a lot of common, everyday, high-speed design problems, but, first we have to get our chip vendors to provide IBIS model files for every part they make. PCD 4/1/1997
Impulsive Behavior sampled data -- Stimulate any linear system with one short, intense pulse, and you see a response characteristic of that particular system. EDN 12/2/2010
In-Between Spaces EM fields, via -- According to Kirchoff’s laws for circuit analysis, the total inductance of two inductors placed in series should equal the sum of their independent inductances; this is not true for parasitic inductances in high-speed digital circuits. EDN 5/24/2007
Inducing Metastability metastability, skew -- What if I *WANT* to induce the metastable state in a flip-flop? Newsletter v4-4 6/4/2001
Initial Condition termination, transmission line -- A split termination biases the line at a halfway voltage so that the driver need only source or sink enough current to swing the line halfway in either direction. EDN 1/10/2008
Intentional Clock Modulation clocks, EMC, jitter -- Over the years, various techniques have been proposed for modulating, or dithering, the clock frequency to break up the accumulated spectral power into a larger number of new modes. EDN 8/3/1998
Intentional Overshoot clocks, overshoot, skew -- Ernie reduces the value of his series terminator, inducing some intentional overshoot that partially compensates for the lack of vivre in the received signal and speeding up (slightly) the threshold crossing. EDN 8/7/2003
Interconnections Matter interconnections -- When you look at a digital machine, if you are not looking at the interconnections, you are missing one of the most important parts of the structure. EDN 5/13/1999
Interplane Capacitance layer stack, power system, return current -- Follow-up to "High-Speed Return Signals" newsletter v1-15, discusses the effective useful radius of the interplane capacitance. Newsletter v3-21 8/30/1999
It's a Gaussian World bandwidth, rise time -- My previous article, "Real Signals" (EDN Oct. 08, 2009), suggests that most digital output waveforms follow a nearly Gaussian profile. Let’s test that theory with a real-world measurement. EDN 1/7/2010
Jitter and Phase Noise clocks, jitter -- Converting spectral-power-density noise measurements into rms and peak-to- peak jitter. Newsletter v4-7 6/25/2001
Jitter and SNR Combined clocks, jitter -- I would rather not consider of the joint probability of occurrence of vertical noise and horizontal jitter in the same equation. Newsletter v7_06 11/18/2004
Jitter Capture jitter, testing -- If you want to measure jitter the same way your receiver sees it, program your jitter measurement equipment to mimic your receiver’s PLL tracking algorithm. Newsletter v13_01 3/19/2010
Jitter Characterization jitter, testing -- I wish I could begin by stating the definition of jitter. Wouldn’t it be great if there was only one definition? Unfortunately, the subject isn’t that simple. Here’s a sampling of definitions from various sources. Newsletter v11_06 10/8/2008
Jitter Creation jitter, testing -- Here is a simple and effective jitter-creation circuit you can use in your own laboratory to create calibrated amounts of jitter. Observing this source, you can try all the features of your jitter-measurement equipment to see what they all do. Newsletter v12_06 10/8/2009
Jitter Measurement jitter, testing -- What is the best way to measure Signal jitter using a Digital Oscilloscope? Newsletter v3-22 10/21/1999
Jitter Tracking jitter, testing -- A deep grasp of jitter, wander, and how a PLL reacts to them will help refine your understanding of serial data communications. Newsletter v13_02 9/3/2010
Jitter-Free Clocks clocks, EMC, jitter -- Is there any way to make a timing reference that has low jitter and low spectral peaks and at the same time is compatible with zero-delay-repeater structures? EDN 8/5/1999
(The) Jitters clocks, jitter -- If you are using a clock multiplier, or a PLL-based clock regenerator, make sure to comply with the specifications for offset, wander, and jitter on the reference clock input. ED 1/20/1997
Keeping Up With Moore management -- multi-layer pc-boards, solid power and ground planes, surface-mount technology, reflow soldering, and the BGA package were the prominent advances in packaging during the last 20 years. EDN 5/7/1998
Killer Packet data coding -- Scrambling by itself does *nothing* to improve the worst case DC balance. Newsletter v5-7 6/7/2002
Law of Product Development attenuation, termination -- Regarding attenuating terminations, "The more independant requirements you place on a circuit, the more complex the circuit must become." Newsletter v8_06 10/3/2005
Line Length reflections, ringing -- The critical line length beyond which many people use terminators varies from about 1/10 to 1/3 the length of the rising edge. Newsletter v3-14 6/7/1999
Linearity EE basics -- Linearity is one of two properties essential for good signal fidelity, audio or otherwise. The other property is time-invariance. EDN 9/9/2010
Logic Analyzer Test Points probes -- The input impedance of the logic analyzer probe… makes a good deal of difference Newsletter v3-2 1/21/1999
Lossless Propagation attenuation, characteristic impedance, dispersion, transmission line -- In the short term, the input impedance of a uniform, lossless, distortionless transmission line appears purely resistive. EDN 12/3/2007
Making Gaussian Edges rise time -- This analog filter network converts each input step into a smooth, Gaussian-shaped rising and falling edge. EDN 12/3/2009
Making Noise power system, testing -- A massive array of sources creates a huge amount of noise useful for testing power supply noise immunity. EDN 9/15/2005
Manager's Guide to Digital Design management -- This one-page executive summary includes everything a manageer needs to know about high-speed digital design. (April 8, 2010). EDN 4/8/2010
Managing Scotty management -- Scotty to Kirk, "We cannot get the shields back in less than an hour, Captain. The Klingon attack cracked our DiLithium crystal, and there’s antimatter leaking everywhere…" EDN 6/7/2001
Margin Testing crosstalk, management, testing -- (by JP Miller) Testing a link in isolation is never sufficient; links must be tested in combination with other noise sources. EDN 3/3/2005
Matching Pads cables, layout, reflections, termination -- The only passive circuits that guarantee good impedance translation for wideband signals are resistive pads. EDN 12/21/2000
Measuring Connectors connectors, crosstalk, testing -- I would like to replace one connector type with a different, less expensive model. How do I prove the two connectors have the same electrical characteristics? EDN 5/10/2001
Measuring Droop power system, probes -- What is the best technique to make DC voltage measurement on a power rail? Will a four-point measurement technique be the most accurate? EDN 2/3/2005
Measuring Power and Ground power system -- Follow-up to "Measuring Power-to-Ground Impedance", nwsltr v2- 14 Newsletter v3-13 5/21/1999
Measuring Power-Plane Resonance power system -- James Mears of National Semiconductor describes his experience attempting to measure the impedance between power-and-ground planes. Newsletter v2-27 10/15/1998
Measuring Power-Ground Impedance power system -- How to convert network-analyzer measurements of the impedance between a pair of power-and-ground planes from dB to ohms. Suggestions on probe configuration. Newsletter v2-14 5/26/1998
Measuring Skew probes, skew -- You can’t depend on automatic de-skewing when measuring tightly coupled differential systems. EDN 2/5/2004
Memory Bus Crosstalk characteristic impedance, crosstalk, jitter -- I am currently working on high speed memory bus with interconnect jitter. My memory team recommends changing the bus geometry to improve timing. Newsletter v9_06 8/22/2006
Metastability in Flip Flops metastability -- What happens if you have two flip-flops in series, both using the same clock, and the first one goes metastable? Newsletter v3-15 7/14/1999
Metastable Persons metastability -- When you violate the setup-and-hold times on a flip-flop, the output might erratically go high, stay low, or pop one way and then back again. EDN 3/16/2000
Millions and Billions back plane, rise time, serial link -- When considering any aspect of your circuit geometry, the relation between physical size and risetime helps determine the relative importance of that object in the overall scheme of the circuit. EDN 8/18/2005
Minimum-Inductance Distribution of Current EM fields, return current -- Faraday, in his mind’s eye, saw lines of force traversing all space. Newsletter v6_07 7/22/2003
Mitigating Crosstalk crosstalk, differential signaling, layout -- What can be done to reduce the amount of crosstalk in a pcb. Newsletter v6-01 1/20/2003
Mixtures of skin-effect and dielectric loss dielectric loss, dispersion, skin effect -- Long, high-speed pcb traces operate in a zone influenced by both skin-effect and dielectric losses. Both mechanisms attenuate the high-frequency portion of your signals, but in slightly different ways. EDN 9/19/2002
Moats and Floats EMC, grounding -- How to conduct multiple comparative layout studies in one pcb fabrication cycle. ED 2/17/1997
Modeling Skin Effect bandwidth, delay, rise time, simulation, skin effect -- Why does high-frequency current flow only on the outer surface of a printed-circuit trace? EDN 4/12/2001
Multi-Level Signaling -- Designcon2000 back plane, multi level, serial link -- multi-amplitude signaling won’t help much below 2.5 Gb/s, however, at higher speeds where the loss slope increases MAS becomes very useful. DesignCon 2000 1/30/2000
Multiple ADC grounding grounding -- Several of you wrote about "ADC Grounding" (EDN, Dec 7, 2000, pg 36) to ask what happens when you have more than one ADC. EDN 2/1/2001
Musical Interference EMC -- When you can walk up to your equipment and make it play Dixie on an AM radio, you will have captured the attention of your digital engineers. EMC Soc Nwsltr 7/1/2002
Mutual Understanding connectors, crosstalk -- A connector configured with too few power and ground pins, or with too many heavy loads, generates a lot of crosstalk. EDN 1/1/1998
Mysterious Ground grounding, probes -- All good probes come with short, tiny ground attachments. For single- ended measurements, don’t depend on mysterious ground connections. Always use a good, short ground connection. EDN 2/7/2002
Nasty ESD Testing ESD, testing -- A thin, plastic package sitting on a metal desk, with wires hanging out the back of the package will prove embarrassingly susceptible to ESD. Newsletter v4-13 10/24/2001
Nature of ESD ESD -- Once inside your product, ESD transient currents spread far and wide regardless of any ground jumpers, 100K resistors, and transorbs that may exist. EDN 8/6/2009
Negative Delay clocks, delay, skew -- If Congress invented negative-delay legislation, it might improve its reputation for alacrity. EDN 8/30/2001
Nibble Effect back plane, transmission line -- A distributed bus simultaneously activates more than one driver. The timing on a distributed bus is as intricately planned as a ballet. Newsletter v12_03 3/26/2009
Nickel-Plated Traces attenuation, skin effect -- We have been advised that due to the changes to the skin effect caused by the Ni/Au on the traces for high frequency RF designs we could be building in a problem. Newsletter v5-6 4/22/2002
Noise Isolation crosstalk, grounding, reference plane -- Achieving isolation greater than 80 dB. Newsletter v2- 13 5/19/1998
Noise Partitioning crosstalk, EMC -- (by W. Michael King) Keep your loud, high-powered partitions from interfering with your little-bitty quiet ones. EDN 3/4/2004
Not all EMC engineers are bald EMC, management -- If you want to keep doing what you love to do you must constantly re- educate yourself. EDN 1/24/2002
Not Your Fault grounding, power system -- Green safety wires do not form a reliable single-point ground reference. EDN 3/5/2009
OFC Madness power system -- Ernie heard that ofc cryogenic power cables are really good, but very expensive ($100’s). Should he buy one? EDN 3/1/2007
On-Chip Bypassing with End Terminations bypass capacitors, chip packaging, power system, termination -- On-chip capacitors have no effect on single-ended systems with symmetrically-split end-terminations. EDN 5/27/2004
On-Chip Bypassing with Series Terminations bypass capacitors, chip packaging, power system, termination -- On-chip capacitors perform brilliantly in a series-terminated architecture. EDN 4/29/2004
Open-Drain Lines open drain, termination -- Should I use one pull-up resistor located somewhere in the middle of my line, or two resistors of twice the value located at each end? Newsletter v2-5 2/9/1998
Operating Above Resonance bypass capacitors, layout -- It’s OK to use a bypass capacitor well above its point of series-resonance. That’s the normal mode of operation for most bypass capacitors. ED 4/14/1997
Parallel Resonance EE basics, power system -- You can determine the peak of a parallel-resonant circuit step response from a graph of its inductive and capacitive asymptotes. EDN 2/2/2012
Parasitic Inductance of Bypass II bypass capacitors -- The following values for the inductance of a surface-mounted bypass capacitor were collected using the step-response technique described in chapter 8 of High-Speed Digital Design. Newsletter v6_09 12/1/2003
Parasitic Inductance of Bypass Capacitors bypass capacitors, layout -- You can estimate the parasitic series inductance of a bypass capacitor in a multi-layer board with solid power and ground planes. EDN 7/20/2000
Parasitic Pads reflections -- It seems that the very short 1-in. trace I’m using is covered more with part pads than with 50-ohm trace. EDN 8/17/2000
Passivation and Solder Mask attenuation, microstrip, skin effect -- Copper traces on outer layers must be protected from corrosion by passivation or by coating them with an inert material. EDN 6/13/2002
PCI Bus PCI -- Discussion of "second-reflected-wave switching" and terminations. Newsletter v2-28 10/22/1998
PCI Series Terminations Resistors delay, multi drop, PCI -- It’s OK to use series termination resistors with bi-directional transceivers. The series resistor just delays the incoming signals and degrades their risetimes. Newsletter v1-4 7/4/1997
PECL Biasing differential signaling, termination -- I thought that PECL outputs always need external resistors to ground since PECL drivers can only source current but not sink it. Newsletter v1-5 7/14/1997
Perfect Probe probes -- The probe I want shows me exactly the signals I need to see without affecting signal quality when I touch the system. EDN 10/14/2004
Persistent Edge return current, rise time -- Are there really any high-frequency currents still flowing in portions of a transmission line after those portions have been passed over by a voltage disturbance moving down the line? Newsletter v8_05 8/23/2005
Picket Fences EMC, grounding -- (by W. Michael King) About the use of a "picket fence" array of ground vias to shield internal sections of a board from each other. Newsletter v2-16 6/8/1998
Placement of End Termination layout, termination -- The sequencing of the end-terminator and its associated load can make a measurable difference in signal quality. Newsletter v2-7 2/25/1998
Planning For Signal Integrity ringing, simulation -- At these extremes of speed, even simple problems, like ringing, can become complex. Check out the nifty new simulation tools now available for dealing with signal integrity problems. ED 5/12/1997
Pointy Tips probes, testing -- Some high-speed oscilloscope probes comes equipped with tips so pointy, so sharp, that you can set them down onto a pcb trace just as gently as a phonograph needle and still pick up a great signal. EDN 5/29/2008
Popsicle-stick Analysis proximity effect, simulation, skin effect, transmission line -- You can model the proximity effect (and see edge-current concentration) using a simple model made from a sheet of rubber and a popsicle stick. EDN 3/7/2002
Potholes reflections -- Adjustments to the width of a transmission line on either side of a heavy capacitive load can partially compensate for the load. EDN 11/11/1999
Power and Ground Resonance power system -- (originally titled: Power Plane Resonance) Your power and ground planes do not form a perfect lumped-element capacitor. EDN 9/1/1998
Power Bus Noise power dissipation, power system -- The CMOS devices that we have looked at can draw peak currents of about an Amp from the power bus (when a single gate switches) if they are connected with a sufficiently low inductance. Newsletter v1-9 8/26/1997
Power of Attraction EM fields, return current -- Suspend a nickel in the air above the battleship Arizona. Remove all the conduction-band electrons from the nickel and place them on the battleship. Newsletter v14_01 2/11/2011
Power Plane Resistance power system, probes -- The DC resistance between any two points within a region of arbitrary shape is easily measured. EDN 7/11/2002
Power Plane Resonance power system -- Your power and ground planes do not form a perfect lumped-element capacitor. EDN 9/1/1998
Power-Ground Source Impedance power system -- This reader takes issue with my claim of having achieved a power-to-ground impedance of 0.01 ohms by paralleling one hundred 0.1uF caps, each having 1 ohm or less impedance at the frequencies of interest. Newsletter v2-4 1/30/1998
Power-On-Reset power system -- Many digital-design teams assign the design of the power-on-reset circuit to their youngest, least experienced engineer. This assignment is a mistake. EDN 12/3/1998
Practical Advice management, testing -- Years ago, an engineer named Allen Goodrich gave me a unique piece of advice. EDN 11/22/2001
Probes probes -- How to accurately probe for noise on power supply nodes. Newsletter v1-13 10/6/1997
Probing for Noise probes -- How can a probe pick up noise when looking at its own ground? EDN 12/4/1997
Probing High-Speed Digital Designs probes -- In high-speed system developments, the ubiquitous 10-pF 10:1 capacitive-input probe is no longer adequate. The two alternatives are the FET-input probe and the resistive-input probe. ED 3/17/1997
Probing Two Points ferrite bead, probes -- You should ground each probe near its respective point of measurement. Newsletter v5-12 9/18/2002
Proximity Effect proximity effect, return current, skin effect -- Is there a "Proximity Effect" in strip lines or microstrips that is caused by currents flowing in adjacent conductors? Newsletter v4-1 3/10/2000
Proximity Effect II proximity effect, return current, skin effect -- Do you have any references dealing… with the current density distribution in a ground plane under a high frequency signal trace? Newsletter v4-3 6/1/2001
Proximity Effect III crosstalk, high-speed digital design formulas, proximity effect, return current -- Justification for crosstalk approximation (see High-Speed Digital Design p. 190, eqn. [5.1]) Newsletter v4-8 10/3/2001
Point to Point Wiring and Big Loads reflections, ringing, wire wrap -- Your best choices are to either slow down the driver risetime a little bit so the whole thing acts as one big lumped-element circuit, or use a real 75-ohm transmission line. Newsletter v3-16 7/21/1999
Pulse Width Compression bandwidth, testing -- A pulse-width compression test overcomes the limitations of probe placement and loading. EDN 3/29/2007
Quadrature Connector Layout connectors, crosstalk, EM fields -- Figure 1 illustrates the blueprint for a differential connector that radically reduces crosstalk between nearest-neighbor pairs. EDN 1/5/2012
Quadrature Via Layout crosstalk, EM fields, via -- No matter where you place a differential via pair, you can always rotate its alignment to mitigate crosstalk from a troublesome differential source. EDN 12/1/2011
Quality management -- Quality is not the result of comprehensive computer simulations. Quality is the result of knowing, through experience, how a product will actually be used in the field and anticipating those needs. EDN 11/3/2011
Quality Factor bypass capacitors -- High-Q capacitors exacerbate resonances in a circuit, and resonance is the last thing you need in a power distribution system. Digital folks want low-Q capacitors. EDN 12/5/2005
Quantization Noise sampled data, testing -- Measurement of low-level analog distortion requires two complementary things: a very good source and a very good instrument for signal detection. Newsletter v9_02 1/12/2006
Radiated Digital Ground Noise EMC, grounding -- Ideally, you should ground your digital logic, the chassis, any cable grounds, and the cable shield (if present) to a common point. Newsletter v2-17 6/26/1998
Rainy-day Fun transmission line -- You can use puddles of water to solve certain difficult problems in the design of high-speed transmission lines. EDN 3/4/1999
Random and Deterministic Jitter clocks, jitter -- The point of separating jitter into random and deterministic components is that the deterministic components have a lower ratio of peak value to standard deviation than do the random components. EDN 6/27/2002
Real Signals bandwidth, rise time -- The step responses of high-speed digital drivers tend to look Gaussian. The same goes for scope probes and pre-amplifiers. EDN 10/8/2009
(The) Real Truth About Crosstalk crosstalk, layout -- If you are trying to manage crosstalk from first principles, so it comes out right on the first spin, look into the new crosstalk prediction tools that feature IBIS I/O modeling. ED 8/18/1997
Really Cool Bus layout, multi drop, termination -- This unidirectional structure supports one driver with many, many loads. EDN 10/26/2000
Reason for Ground Split crosstalk, grounding -- There are indeed applications so sensitive that they require separation of the analog and digital ground regions. Newsletter v9_04 3/24/2006
Reducing EMI with Differential Signaling differential signaling, EMC -- You need not struggle to place ordinary differential digital traces any closer than 0.5 mm for any EMI purpose. EDN 12/12/2002
Reducing Emissions EMC, termination -- (by Bruce Archambeault) Most radiated emissions problems depend more on signal currents than signal voltages. The source-termination resistance controls both received signal amplitude and drive current. EDN 3/1/2001
Reference-Free Pair characteristic impedance, differential signaling -- An "image plane" method calculates the impedance of an over/under configuration with no solid reference plane. EDN 7/20/2006
Relevance of Physics electromigration, management, power dissipation -- The engineering curriculum for first-year students at Oxford University still includes a good amount of basic physics, despite attempts by computer scientists at other universities to de-emphasize that subject. EDN 5/1/2003
Resistance high-speed digital design formulas, power system -- Regarding page 414, equation for calculating the DC resistance of power planes based on the diameters of two contact points space at X amount of distance. Newsletter v1-11 9/15/1997
Resonance in Short Transmission Line ringing, termination -- The resonant frequency and Q of a short, unterminated line varies strongly with capacitive loading. Newsletter v6-06 4/14/2003
Return Current in Plane return current -- Distribution of return current on the solid plane underlying a high-speed signal trace. Newsletter v3-11 4/26/1999
Return Current Matters differential signaling, return current -- Differential architectures sometimes tempt us to ignore return current issues… [but] even in a differential configuration, current flows on the planes under each trace separately. EDN 9/16/2004
Ribbon Cable Impedance cables, differential signaling -- The impedance of flat-ribbon cable depends on the pattern of grounds. Newsletter v3-10 4/6/1999
Ringing in a New Era ringing, simulation -- From this day forward there is absolutely, completely, totally no longer any excuse whatsoever for system problems, glitches, data errors or other artifacts related to ringing in digital signals. EDN 10/9/1997
Risetime of Lossy Transmission Line cables, rise time -- The risetime of a long skin-effect limited cable scales with the square of its length, not according to the sum-of-squares rule for [the risetime of] cascaded linear systems. EDN 10/2/2003
Rising Problem bandwidth, reflections, ringing -- The Gaussian edge best represents actual digital logic. It displays virtually no perceptible ringing in the time domain—just like the real circuit Newsletter v9_05 6/16/2006
Rollback RoHS management -- Lead-free solder is not a "green" solution. Lead-free solder actually damages the environment more than 60/40 solder. Newsletter v10_01 4/16/2007
Scattering Parameters reflections, simulation -- Relates S-parameter matrices provided by a network analyzer to transmission-matrices used for simulation work. Newsletter v6_03 2/17/2003
Scrambled Bus data coding, EMC -- The improvement in common-mode radiation from the straight, unencoded, worst-case example to the best scrambled-and-coded version is better than 30 dB. Newsletter v7_10 12/14/2004
Scrape It microstrip, probes -- I only know six ways to remove solder mask for probing: Scraping, milling, grinding, micro-blasting, chemical stripping, and ultraviolet (UV) illumination. EDN 5/1/2008
Second-Level Interconnects interconnections, system-on-a-chip -- A reader suggests, "The days of discrete design and interconnect are rapidly disappearing, if not gone already." Newsletter v2-15 6/4/1998
See Beyond the Edge characteristic impedance, testing -- The far-end reflected signal is usually considered the end of usable data in a TDR waveform, but a wealth of information lies beyond this point. EDN 10/13/2005
Segmenting the Vcc Plane EMC, ferrite bead, power system -- I don’t cut up the Vcc plane unless I have one circuit that is substantially more sensitive to Vcc noise than the other circuits on the board. Newsletter v2-18 7/23/1998
Serial Killers data coding, serial link -- If you are responsible for selecting a serial interface standard, I’d like to pass along a few ideas for your selection criteria, starting with some concepts having to do with the physical link protocol, particularly DC balance. Newsletter v7_07 12/1/2004
Serpentine Delays clocks, delay, skew -- If you are using some form of delay line to match clock delays at all points of usage within a pc board, here’s a short list of the items you need to match: EDN 2/15/2001
Setting the Standard for Gigabit Ethernet Gigabit Ethernet -- The Gigabit Ethernet standard provides for a number of physical layer transmission interfaces. ED 6/23/1997
Settling Time Measurements delay -- What is the correct method to measure the settling time of a digital waveform? Newsletter v3-17 7/28/1999
Seven Percent Solution termination, testing -- The distribution of 10%-resistor values in a bin does not follow a simple Gaussian profile. EDN 6/10/2010
Severe Overshoot overshoot, ringing -- Will overshoot and undershoot impact the receiver, damage it or cause excessive recovery time? Newsletter v2-31 12/2/1998
Severe Overshoot Mailbag overshoot, ringing -- ...the clamp diodes shot current into the VCC net… …make sure you are measuring the overshoot correctly… ...Undershoot on some lines on some SRAM chips will cause "weak writes"… Newsletter v3-1 1/14/1999
Shannon Says connectors, crosstalk, multi level -- Connector vendors will soon realize that great improvements in the information-carrying capacity of their products may be had by reducing crosstalk. EDN 11/13/2003
Shaping Edges rise time, sampled data -- If you have a record of a driver’s actual output signal shape, or can extracted it from an IBIS file, use it. In the absence of other information, assume a Gaussian shape. EDN 11/12/2009
Sharp Edges ringing, simulation -- A PWL edge over-stimulates the resonant behavior. A smooth Gaussian edge better represents a real digital signal, eliminating phantom ripples in your simulation output. EDN 6/22/2006
Short Transmission Line Model transmission line -- Lumped-element modeling of transmission line behavior using the "PI-Model" Newsletter v3-18 8/7/1999
Short-Term Impedance of Planes EM fields, power system, return current, via -- Doesn’t the returning signal current just pop between the planes through the parasitic capacitance of the planes themselves, you might ask? Newsletter v6_05 3/24/2003
Shot Heard 'Round the World reflections, ringing, termination -- Let’s apply Sabine’s theory of acoustic reverberation to a digital problem. EDN 10/16/2008
Signal Ground Drain Wire cables, connectors, EMC, ground bounce -- Why should disconnecting the "drain wire" at the connectors have such a drastic impact on the rise/fall time of the outer conductors? Newsletter v2-32 12/4/1998
Signal Integrity Mailbag clocks, EMC, jitter -- My recent column on intentional clock modulation (EDN, Aug 3, 1998, pg 24) spurred some interesting responses from readers. EDN 10/8/1998
Simulation Software EMC, simulation -- What are the primary issues at hand, and what are the important questions to ask before you get yourself mired in a project that may not pay off. Newsletter v1-16 11/4/1997
Single Point Ground grounding -- Moat-and-drawbridge approach used on mixed-signal board. Newsletter v2-26 9/29/1998
Skin Effect Calculations skin effect -- Derivation of skin-effect loss equations in High-Speed Digital Design Web
Skin Hot skin effect -- How skin resistance changes with temperature. EDN 3/6/2003
Sliding Edge reflections, transmission line -- When you connect two boards made from dissimilar fiberglass laminate materials, will high-speed signals reflect due to the sudden change in board properties as they move across the connection interface? EDN 9/3/2009
Slippery Slopes differential signaling, skew -- Differential Skew revisited: skew disperses your risetime, increasing your susceptibility to jitter caused by additive noise. EDN 4/1/2004
Slow Wave Mode delay, transmission line -- The slow-wave effect hampers signal transmission on some on-chip MIS (metal-insulator-semiconductor) interconnections. EDN 11/8/2001
So Good it Works on Barbed Wire cables, transmission line -- Next time you look at a transmission line, I hope you’ll focus on the big four properties: characteristic impedance, high-frequency loss, delay, and crosstalk. EDN 7/5/2001
Software Crosstalk crosstalk -- Explains why software tests for ringing and crosstalk are necessary and what specific features are needed. Newsletter v5-0 6/24/2002
SONET data coding data coding, level translation -- Figure 1 shows one way to build a non-linear DC restorer. This circuit fixes the DC balance of a SONET data string that has lost its DC level because of AC-coupling. Newsletter v5-5 3/29/2002
(The) Sound of Progress back plane, connectors -- The vias and breakout patterns underneath a connector control its physical scale and thus its electrical performance. EDN 5/12/2011
Space-Time Diagrams back plane, transmission line -- Where the waves cross, at each point in time and space the transmission line sums their amplitudes. Like rogue waves crossing in the middle of the ocean, the effective total height of the combination may exceed that of either wave alone. Newsletter v12_02 1/25/2009
Specsmanship management -- Every Joe at the lumberyard understands that a 2x4 does not measure two inches by four inches. EDN 2/2/2006
Spotlight Interview with Dr. Howard Johnson management -- Dr. Johnson responds to questions from the EE Web staff about technology, it’s direction, the importance of early education, and the influence of parents and mentors. This article is reprinted in honor of his father, Dr. Jim Johnson, 1932-2012. Web 2/21/2012
Spread Your Returns crosstalk, ground bounce -- BGA package analysis; Signals closest to a good return suffer the least ground bounce. EDN 3/31/2005
Squeeze Your Layer Stack back plane, dielectric loss, via -- Given the same trace width and trace impedance, a lower dielectric constant lets you squeeze the layer stack. Newsletter v7_04 9/1/2004
Star Topology ringing, termination -- A star topology connects N devices in a completely symmetrical, peer-to- peer fashion. EDN 11/11/2004
Steel-plated Power Planes power system, reference plane -- A thin coating of steel, applied to the inside-facing surfaces of a power and ground plane pair may help damp power plane resonance. EDN 3/21/2002
Step Response Test connectors, probes, testing -- My favorite repetitive step response stimulus is a simple square wave with 50% duty cycle. (This article includes many details of measurement technique and interpretation.) Newsletter v11_01 3/13/2008
Straddle-Mount Connectors chip packaging, connectors -- Follow-up to "Tapered Transitions", EDN 11 Oct., 2001 Newsletter v4-18 12/19/2001
Strange Microstrip Mailbag dispersion, microstrip, transmission line -- Follow-up to April 26, 2001 column in EDN, "Strange Microstrip Modes." Newsletter v4-16 11/28/2001
Strange Microstrip Modes bandwidth, overshoot, TEM mode, transmission line -- "Quasistatic" values of capacitance and inductance are the values you get at low frequencies, near dc. EDN 4/26/2001
Stub Termination termination, via -- (by Lambert (Bert) Simonovich) A via-stub termination can eliminate via resonance at the expense of a modest amount of flat-loss attenuation. EDN 5/13/2010
Stubs & Visas reflections -- I would like to know the effects of stubs and vias in high-speed PCB designs. Newsletter v2-25 9/16/1998
Submicron ASICs and EMI-EMC chip packaging, EMC -- Above Fk the limited rise/fall time in your chips provides a natural filtering effect that limits emissions. EDN 4/13/2000
Superposition EE basics -- Linear superposition opens the door to many advanced methods of circuit analysis. EDN 10/7/2010
Surface Roughness attenuation, surface roughness, transmission line -- At a microscopic scale, no surface appears perfectly smooth. EDN 12/6/2001
Synchronizing clocks clocks, skew, synchronization -- What should I do to prevent noise problems if I choose not to synchronize the whole clock tree. Newsletter v4-6 6/19/2001
Take the Fifth EE basics, rise time -- How many harmonic terms must I take to adequately represent a good squarewave? EDN 2/3/2011
Tapered Transitions characteristic impedance, connectors -- Consider the problem of adapting a straddle-mount SMA connector for a 10-Gbps digital application. EDN 10/11/2001
TDR and Ice Cube Trays return current, transmission line -- The "Ice Cube Tray" model of distributed transmission. Newsletter v3-5 2/5/1999
Ten Layer Stack layer stack, return current -- Discussion of multi-layer board stack for system with multiple power voltages. Newsletter v2-11 4/27/1998
Terminator Crazy return current, termination -- The first clue as to whether a terminator is needed is the ratio of trace delay to rise time. ED 10/1/1996
Terminator I reflections, rise time, termination -- If you can limit the magnitude of the reflections to, say, x percent of the signal swing, then the worst-case time-domain jitter induced by those errant reflected blips will amount to only a x percent of the signal risetime. EDN 3/2/2006
Terminator II reflections, rise time, termination -- Resistor R2 acts as an isolation component, preventing the FPGA capacitance from directly loading the terminating resistor. EDN 3/30/2006
Terminator III reflections, rise time, termination -- I want to force the apparent termination impedance to equal precisely 50 ohms, with minimum degradation of the received signal risetime. EDN 4/27/2006
Think Small chip packaging, EM fields, rise time -- The three-dimensional rule for physical scaling of electrical connections immutably controls the performance of connectors, packages, component bodies, vias, and many other common structures. Newsletter v8_04 5/4/2005
Three Drop Bus layout, multi drop, power dissipation -- The three privileged locations on a long net are at one end, the other end, and right smack in the middle. Newsletter v4-12 10/18/2001
Through-hole Clearances connectors, crosstalk, Ernie -- Connectors require continuity of the ground plane underneath the connector. EDN 7/8/1999
Time Invariance EE basics -- Hard clipping obeys time-invariance, but not superposition. A tremolo circuit obeys superposition, but varies its gain with time. EDN 11/4/2010
Tiny Difference layout, probes, skew -- Measuring a tiny time difference like 5 ps can be quite challenging. Anjaly will need well-matched, skew-calibrated probes and perfectly symmetric attachments to the board. Newsletter v9_08 12/21/2006
Tips on Controlling Clock Skew clocks, skew -- Your ability to manage and control clock skew has been recently improved by the introduction of a new generation of multi-output, low-skew clock drivers. ED 7/21/1997
To Tee or Not To Tee? layout, multi drop -- The basic problem with this topology is that all three branches are long compared to the length of a rising edge. EDN 2/2/1998
(The) Torches and the Hair bandwidth, multi level, serial link -- Mankind has a long history of experience dealing with bandwidth-limited communication channels. DesignCon 2003 2/17/2003
Trace Between Capacitors crosstalk, layout -- Will crosstalk occur if I route a trace underneath a bypass capacitor? Newsletter v3-4 1/28/1999
Trace Inductance transmission line -- Can you give me a basic (approximate) formula for the inductance of (1) a bare pc trace, and (2) A trace suspended above an adjacent plane. Newsletter v3-8 3/23/1999
Trace Scaling simulation, skin effect -- How to circumvent minimum feature-size limitations in your SI simulation tool. EDN 3/4/2010
Transmission Lines/Gate Delay transmission line -- What does this mean: "Until the driver becomes aware of the impedance mismatch at the end of the line the line looks resistive" Newsletter v1-19 12/4/1997
Transmission-line Scaling bandwidth, transmission line -- Every pc-board trace has a limited bandwidth. As chips go faster and faster, you eventually run into this limitation. EDN 2/4/1999
Tricky DRAM Lines layout, multi drop -- The app note I’m looking at suggests that my DRAM address lines run in a "T" shape… with a ground plane cut under the DRAMs Newsletter v1-20 12/15/1997
Twisted Crosstalk crosstalk, EM fields -- Differential links have a good reputation for rejecting external noise. Unfortunately, that good reputation extends only to noise that affects both wires equally. Newsletter v12_01 1/9/2009
Twisted Impedance characteristic impedance, differential signaling -- When separation, S, is less than wire diameter, D, doesn’t your formula ln(2S/D) return a negative value for characteristic impedance? What gives? EDN 9/18/2008
Two-way Street probes, simulation -- Transmission lines, like streets, support traffic in two directions. A voltage probe shows only an aggregate voltage waveform, but doesn’t say which way the waveform is moving. EDN 1/4/2007
Uncertainty Principle bandwidth, rise time, testing -- The shorter the duration of an event in time, the wider must be the spread of frequencies associated with it. EDN 7/19/2007
Undo Machine EE basics, equalizer, sampled data -- The signal distortion caused by some linear time- invariant processes can be completely un-done. EDN 1/6/2011
Unified Eletrodynamic Force EM fields -- The magnetic force is nothing more, and nothing less, than a direct consequence of Einstein’s theory of relativity. EDN 2/5/2009
Using Ferrites crosstalk, ferrite bead -- If two or more ferrites are placed parallel and close to each other will this result in crosstalk between them? Newsletter v1-2 6/13/1997
Value of End Terminator EMC, termination -- Should an end-terminator always be set at the highest value that works because that minimizes the current and therefore gives the best EMI performance? Newsletter v5-1 1/7/2002
Via Capacitance via -- Formula [7.6] in High-Speed Digital Design for the capacitance of a via is a crude approximation. I’ve now got some better material. Newsletter v5-9 7/15/2002
Via Inductance EM fields, high-speed digital design formulas, return current, via -- The inductance of a via depends on the path of returning signal current. Newsletter v6-04 3/15/2003
Via Inductance II via -- Corroborates real-world measurements of via inductance with a simple approximation. Newsletter v6_08 9/10/2003
Visible Return Current return current -- I may at last have found a way to demonstrate, in a direct (and dramatic) fashion, to any observer, where and how high-frequency current flows in a printed circuit board. Newsletter v8_08 12/1/2005
Visualizing Differential Crosstalk crosstalk, differential signaling -- The spacing between the wires of a differential stripline pair affects crosstalk only mildly EDN 12/5/2008
Voltage Conversion attenuation, termination -- James Buchanon points out that my attenuating terminator may be impossible! Newsletter v9_01 1/4/2006
Voltage Regulator Droop power system -- When the load draws current, the new larger value of regulator output resistance will increase the droop measured at Vcc. That sounds bad, but in some very special circumstances it is actually good for your circuit. EDN 9/14/2006
Voltage Regulator Model bypass capacitors, power system -- One step-response test reveals enough information to form a simple circuit model of most any voltage regulator. EDN 8/17/2006
VRM Stability - Part I: Feedback crosstalk, power system -- Feedback must be carefully controlled because, by its very nature, feedback invites the risk of self-oscillation. Newsletter v10_3 9/10/2007
VRM Stability - Part II: ESR bypass capacitors, power system -- The ESR of your VRM output capacitor controls both its ripple amplitude and stability. Newsletter v10_4 9/17/2007
Wafer-Probe Launch layout, testing -- At 28-Gb/s the SMA runs out of gas, so connect your VNA to the layout test card using a high-performance microwave wafer probe. EDN 10/6/2011
Water Analogy EE basics -- Pump A forces water at constant pressure p1 around a closed loop controlled by valve B at a steady velocity v1. This is the law of EDN 7/15/2010
Water Hammer EE basics, Ernie -- A system of water pipes with a large electric snap-action water valve and a flow regulator explodes at midnight. EDN 8/12/2010
Watery Grave ESD -- Design your system to survive near-miss situations. The most common near-miss scenarios include discharges to your product chassis, the wires leading into or out of your chassis, or metallic objects near those wires. EDN 6/23/2005
(The) Way Home bypass capacitors, layout -- Current always makes a loop. If it goes out, it must find a way back home. The shapes of both the outgoing and the return paths affect the observed inductance. EDN 6/22/2000
Way Too Cool management, power dissipation -- LED traffic lights clog with snow, become indiscernible, and cause fatal traffic accidents. EDN 2/4/2010
Whang That Ruler ringing, termination -- A capacitive load applied to a pcb trace lowers its resonant frequency much like a quarter taped to the end of a ruler lowers its resonant pitch. EDN 4/7/2011
What's That Glitch? reflections, transmission line -- Have you ever seen a non-monotonic glitch in a signal like the one shown in Figure 1? Can you guess what causes it? EDN 8/19/2004
What's That Plateau? probes, termination, transmission line -- An unexpected plateau implies the presence of a transmission line stub. Newsletter v7_03 6/14/2004
When Everything Matters management -- Squeeze that last drop of performance from a CMOS architecture by turning up the clock or adding a few new features and you may choke on the curse of complexity—where every decision you make interacts with every other decision. EDN 1/6/2005
When Logic Switches Too Fast rise time -- When new chips are substituted into older designs, the new, faster chips may bring you nothing but headaches. ED 7/1/1996
When to use AC Coupling clocks, interconnections, level translation -- When should one adopt DC coupling versus AC coupling? Newsletter v4_15 11/13/2001
Who's Afraid of the Big, Bad Bend? microstrip, reflections, transmission line -- Right-angle bends in PC-board traces perform perfectly well in digital designs in speeds as fast as 2 Gbps. EDN 5/11/2000
Why 50-Ohms Mailbag cables -- Regarding my article "Why 50 Ohms?" (EDN, Sept 14, 2000, pg 30), I received some interesting justifications for the use of 50-ohm coaxial cabling. EDN 1/4/2001
Why 50 Ohms? cables, transmission line -- Why do most engineers use 50-ohm pc-board transmission lines? Why not 60 or 70 ohms ? EDN 9/14/2000
Why Digital Engineers Don't Believe in EMC EMC -- Digital engineers don’t believe current flows in loops, existence of the H-field, gates are differential amplifiers, existence of EM waves, or that EMC will advance their careers EMC Soc nwsltr 3/2/1998
Why is That? reflections, termination -- You need three things: Good measurement equipment, a simulation system handles your application, and knowledge of what factors might reasonably affect your design. I teach the knowledge part. Newsletter v11_05 9/2/2008
Why Johnny Can't Design a High-Speed Digital System management -- As a class, digital engineers are less well equipped now than they were 30 years ago to design a high-speed digital system. DesignCon 2003 2/17/2003
Why Teach Science? management -- Science is not for everybody. You could live like an aborignal, running around naked in the forest chasing deer with bows and arrows, for all I care. EDN 2/1/2007
Winsome Waveform Wizardry management -- This fast-paced podcast appearance with Chris Gammel on the "Amp Hour" touches on many of the finer points of life, including how to hide technical details from your boss, how to get a standard through the IEEE, and dealing with unwelcome co-workers. Web 1/9/2012
Wire-Wrap wire wrap -- What are other simple ways of connecting two ICs together that are more robust than wire-wrap? Newsletter v2-8 3/5/1998
Words of Wisdom management, testing -- What instructions would you give to a development team working on a 10 Gb/s serial link? EDN 4/3/2003
Working with EMC Consultants EMC -- The biggest EMC mistake you can make is the failure to get your consultant involved at a sufficiently early stage. Newsletter v5-10 9/10/2002
Yao! What a Handshake level translation, termination -- Making the output voltage equal VT is the easiest thing in the world for a driver. The terminating voltage is a "natural resting place". If you disconnect the driver, the load immediately relaxes, all by itself, to VT. EDN 2/7/2008
Your layout is skewed differential signaling, skew -- Chamfering or rounding of differential corners does not eliminate skew. EDN 4/18/2002
Z[min] level translation, termination -- Understanding Z[min], dear reader, is the secret to successful end-termination design. EDN 2/27/2008