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Bypass Capacitor Layout
(Originally
published in Printed Circuit Design
Magazine, August, 1997)
For as far back
as most practicing engineers can remember, the speed and
density of digital logic has just about doubled every
three years. Between 1974 (the first year of introduction
for the 8080) and 1997 the speed of operation for typical
microprocessors has rocketed up from 200 KHz to 200 MHz.
It's an industry-wide trend, and it's unstoppable:
customers demand speed.
If the speed of
operation has changed by that much, you would think that
the role of the bypass capacitor would have changed
dramatically, too. It hasn't. This lowly component is
still used in the same basic way, for the same basic
purpose, as it was twenty-three years ago. It's time for
a change.
Why
change is necessary
As logic speeds
have spiraled upward, the frequency content of a typical
digital signal has moved up into the gigahertz range. The
performance of bypass components, which are expected to
safeguard the power system against signal-induced
fluctuations, must now be extended up into the same
range. Yesterday's design rules, adequate for use at low
speeds, are not a good match for today's screaming-fast
logic.
The primary
symptoms of an inadequate, old-fashioned bypass capacitor
array are increased power supply noise, increased
crosstalk among signal traces, and increased
electro-magnetic radiation. Power supply bypassing is a
serious matter that merits serious attention. Digital
design shops that have not reviewed their bypass
capacitor design rules in several years would do well to
take a close look at the issue.
Electrical
Performance Of Bypass Capacitors
The subject of
bypass capacitor layout has ramifications for both
electrical and mechanical design. The primary electrical
design issue has to do with what is called the
"parasitic series inductance" [ed. note: please
use italics instead of quotes] of the bypass component.
The parasitic series inductance of a bypass component
acts like a little inductor wired in (guess what) series
with the component. At higher and higher frequencies, the
impedance of this little parasitic inductance becomes
larger and larger, until it dominates the performance of
the component.
In the critical
100-1000 MHz band, the effectiveness of a typical bypass
capacitor is determined almost entirely by its series
inductance. This is the frequency band now being used
increasingly by digital logic.
(FOOTNOTE 1) For good
performance we want low series inductance. The series
inductance of a bypass component is determined almost
entirely by the layout of the capacitor's mounting pads
and its associated vias. Every time we double the logic
edge rates, we become twice as dependent on these layout
details.
Series inductance
is impacted unfavorably by any of the following:
- Long traces
(> 0.01 inch) between the capacitor pads and
vias
- Capacitor
mounting arrangements that stand the capacitor
body up away from the board,
- Capacitors
with any sort of mounting configuration other
than surface-mount pads, and
- Skinny via
holes (less than 0.035 inch diameter).
On the other hand,
series inductance is impacted favorably by
- Surface-mount
configurations using wide, squat mounting pads
with vias jammed up next to the pads (no traces),
- Great big
via holes, and
- Thin boards
(less than 0.030 inch thick) that bring power and
ground planes right up near the body of the
capacitor.
Series
inductance is a real and measurable effect. On a bare
board (bypass capacitors only), an RF engineer can use a
network analyzer to make a plot of the power-to-ground
impedance versus frequency for the assembled bypass
capacitor array. This is a good measurement to take. The
impedance plot will clearly show a region around 1 MHz
where the impedance, as a function of frequency, is going
down. This is the region where the bypass capacitors are
doing their best job.
The plot will
then show another region around 100 MHz where the
impedance, as a function of frequency, has hit bottom,
turned around, and begun heading back up. That is the
region dominated by series inductance (which is
determined by layout).
At the highest
frequencies (1000 MHz and above) the impedance tops out,
turns around, and heads back down again. This is the
region dominated by the natural capacitance between the
power and ground planes (if you have them). This
inter-plane effect is, for most practical purposes, an
ideal capacitance.
If a finished
product suffers from too much noise in the 100 to 1000
MHz region, the best, most effective way to reduce noise
in that region is to improve the layout of the bypass
capacitor pads and vias. Improving their layout reduces
the effective inductance of the parts, leading to a
direct reduction in power and ground noise. If you can't
improve the layout, try these other ideas:
- Add more
bypass capacitors to the board (this costs money
and takes up space for parts).
- Change to a
more effective style of part. For example, look
for the new side-ways mounted 0612-style (as
opposed to 1206-style) surface-mounted
capacitors, or the broad, flat packages offered
by Circuit Components, Inc., or the new AVX brand
LICA style capacitors. Some of these parts offer
an effective inductance 20 times as effective as
a single 1206-style part.
- Reduce the
logic switching currents by reducing the loads on
each gate, or reducing the number of
simultaneously switching gates.
If none of the
above approaches work, you can try using a
higher-dielectric-constant material between the power and
ground planes (Zycon is one brand name that comes to
mind), or stacking the power and ground planes closer
together. These last alternatives tend to influence the
power-to-ground impedance mostly at the upper part of the
range, from 500 MHz up.
Conclusions
Good bypass
design plays a critical role in the control of power and
ground noise, crosstalk, and electromagnetic radiation.
If you are having problems with these issues in the 100
to 1000 MHz band, take a look at the effective series
inductance of your bypass capacitors. The problem may lie
there. If your designs are working well today, and
bypassing is not a problem, don't get complacent.
Progressive advances in the speed of digital logic will
cause problems soon enough. Continual adjustment of
bypass capacitor placement and routing rules is the only
safe course of action.
(FOOTNOTE 1): The frequency content
of a digital signal extends mostly from DC up to a
frequency equal to one-half divided by the 10-90% rise or
fall time of the signal. For example, a digital signal
with 1-ns rise/fall time has a frequency content that
extends up to 500 MHz. The frequency content is a
function of the edge speed, not the clock rate. Forget
about harmonic analysis. We are talking here about real,
digital, non-repetitive signals.
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