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Dr. Johnson's Signal
Integrity Lab (SiLab)
As Dr. Johnson continues to produce SiLab
videos, he wants your feedback about which
topics you'd like to see next. Here is a
list of a few of the topics that have been
requested. If you have additional ideas for
topics or would like to "vote" on one of the
topics below, then please
contact us.
1.
Parasitic Inductance of a bypass
capacitor
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The pads and vias
associated with a surface-mounted bypass
capacitor exert tremendous influence over
its high-frequency performance. This
laboratory session presents a simple
intuitive model of the electrical behavior
of pad and via structures, illustrating in a
direct way the importance of good
layout.
Quantitative measurements
of the inductance of particular
surface-mounted bypass capacitor layouts
appear in the video. After watching this
session you will be able to just look
at a surface-mounted structure and estimate
its inductance.
Point to remember:
layout significantly affects the performance
of bypass capacitors.
Each via on your pcb
exhibits both capacitive and inductive
effects. This session focuses on the
inductive properties of an individual
multi-layer via.
Dr. Johnson constructs a
working large scale model of a via, large
enough so the he can reach into the board
and modify the structure from within while
observing, in real-time, the electrical
behavior of the via.
The presentation
emphasizes the importance of good interplane
connections near those locations where
high-speed signals traverse vertically
through your layer stack.
Point to remember:
The position of your interplane connections,
whether they be formed from vias or bypass
capacitors, affects the performance of
signal vias.
What happens when you
violate the setup and hold times on a
flip-flop? Sometimes it goes to one,
sometimes it goes to zero, and sometimes -
this is the subject of metastability - it
takes a long time to make up its mind.
Dr. Johnson demonstrates
the principal of metastability in a direct
and unambiguous way, leaving you with a deep
and lasting understanding of why the effect
happens, how it behaves, and what you can do
to manage its impact on system reliability.
Point to remember:
Use the slowest practical clock for a
synchronizing circuit, and then add a two-
or three-stage synchronizer if necessary.
4.
S-parameters
Define what it means for
a circuit to be linear and time-invariant.
Explain why s-parameters are not directly
useful for non-linear analysis. Discuss
small-signal linear parameterization of
non-linear circuits. Define the s-parameter
matrix. Show examples of measured
s-parameters for various simple circuits.
Compare the s-paramter information to TDR
and TDT measurements. Explain how the
measurements are equivalent, and show the
conversions between them. Discuss why you
can't just combine S21 measurements to
predict the performance of a complex circuit
(because that procedure ignores the
reflections). Show how cable calibration is
done. Discuss examples of when cable
calibration might not work properly, and
discuss how to know when you are approaching
that limit.
Point to remember:
S-parameters are one of many ways to
characterize a linear system.
5.
Differential S-parameters
A sequel to
"S-parameters"
Define the differential
s-parameter matrix. Outline the
circumstances in which this matrix might be
useful (especially extraction of just the
differential-to-differential terms). Show a
series of "null experiments" you can use to
determine whether the probes and their
connections to your system are truly
well-balanced. Discuss the shortcomings of
some "de-skewing" procedures.
Point to remember:
Differential systems must be measured with
odd-mode (differential) signals.
6.
De-embedding (a.k.a. peeling, or
de-convolution)
Discuss the basic premise
of de-convolution (as first used in the oil
industry for seismic exploration). Show the
limitations of the technique. Discuss the "lossless
network" assumption. Discuss problems with
the "noise floor".Discuss the difficulty of
producing a simple circuit model for a
de-convolved piece of a system. Conclude
with advice on when the technique will
likely be successful.
Point to remember:
De-embedding, like many forms of
extrapolation, is helpful but works best
when you don't have to do very much of it.
7.
TDR test techniques
Probe fixtures, SMA
launch, and the effect of cables. Go through
the "calibration" routine, showing what it
can and cannot do. Show the importance of
using a reasonable risetime (or
post-filtering to display a reasonable
risetime). Conclude with advice on how to
tell when the technique is providing useful
information.
Point to remember:
The better your launch conditions the better
your TDR results.
8.
SMA launch optimization for TDR
testing
Design and test several
layouts for SMA test connectors.
Point to remember:
The details of SMA layout patterns
significantly affect performance.
9.
The need for speed
Premise: "Every design
group needs up-to-date test equipment."
Use a business analogy for managers: "You
can't run Wal-Mart without accurate
inventory control."
Obviously,
accurate measurement of business parameters
is an essential part of running any
low-margin business.
Digital
designs, if you wish to approach the upper
limits of speed and performance, work in a
similar way. One must push the design to the
absolute limit of performance without
actually falling off. Show slides and
lecture material from DesignCon 2004
"Approaching the edge" (this is about
designing things that are guaranteed to be
reliable, but operate very near the edge of
maximal possible performance, hence the
pictures).
Show specific examples of
problems in digital design created by
inadequate equipment (i.e., without adequate
bandwidth and probes you can't measure
jitter, or see ringing, or measure
compliance with eye patterns). Relate this
discussion to the cost of product design
failure and the delay of new product
introduction.
Conclude with a
discussion of the general types of equipment
necessary for high-speed design work, and
questions you can ask of your engineers to
make sure they are being realistic in their
requests for equipment.
Point to remember:
You can't design high-speed systems without
good high-speed test equipment.
10. Probe modeling
Shows how a probe
distorts your signal in two ways. First, the
input impedance of the probe loads your
circuit distorting the actual signals
within. Measure the input impedance of a
scope probe with both VNA and TDR.
Second, the transfer
function of the probe and vertical amplifier
further modify the appearance of the signal
under test. Measure the transfer function.
Show an example of a poor
probing technique -- the long ground wire.
Show an example of a good probing technique
-- a small test point with ground relief.
Discuss why simple rms rule for adding
risetimes doesn't work for some advanced
probes.
Point to remember:
It is possible to de-convolve the effects of
probe loading and bandwidth if you have a
good enough probe model.
11. Differential probing
Outline the main features
of differential probes, including
common-mode noise rejection. Show how the
input impedance of a probe is noticeably
affected by how it is held, and how the test
points on the board are configured. Explain
why a common-mode ground connection between
your system and the scope is beneficial.
Show what modes of noise pickup are
different between single-ended and
differential probes. Discuss when
differential probes are advisable (and
necessary) for probing single-ended signals.
Show an example of a single-ended system
that benefits from differential probing.
Point to remember:
Differential probes aren't useful only for
measuring differential signals.
12. Linear filter theory
- convolution
A sequel to "Time and
Frequency".
The convolution integral,
how it works, and what it means.
Correspondence between time analysis and
frequency analysis. What a linear filter can
do and what it cannot. Application of filter
theory in determination of ISI for serial
datastream.
Point to remember:
A low-pass filter has a dispersive effect on
signal risetime.
13. Noise floor
Measurements of 5V
digital signals made at 10 MHz are so far
above a normal oscilloscope noise floor that
you hardly give the noise floor a second
thought. This principle is not true at
10 GHz.
Show how to measure the
noise floor of a probe or scope. Show the
relation of the noise floor to the
configuration of the probe. Show how to
determine if extraneous noise sources are
influencing your measurements. Show how
averaging reduces the noise floor -- but
only for synchronous signals. Show how
trigger stability influences observed
jitter.
Point to remember:
A lower noise floor makes a better,
higher-resolution measurement.
14. Trigger stability
Measure the stability of
a trigger circuit. Show its immunity to
various influences (how it filters incoming
jitter, for example). Calculate the
stability required to accurately measure
jitter on serial-data waveforms at 10 GHz.
Compare the required stability with
available equipment.
Point to remember:
Trigger stability is paramount when
measuring jitter.
15. What causes jitter
Begin by discussion
general sources of noise. Use as an
illustration an audio amplifier, so you can
"hear" the noise. Listen to thermal noise
(very quiet). Hear microphonics (noticeable
when banging on the system or vibrating it).
Demonstrate an amplifiers with a poor noise
figure (much louder). Add power-supply noise
(overwhelming hum).
Show how these same
things afflict oscillators. Show how to
"demodulate" the oscillator so you can "see"
its phase noise on a scope.
Point to remember:
Jitter behaves like any other form of noise.
16. Measuring
deterministic jitter
Create a serial
datastream signal with deterministic jitter.
Capture the waveform and define the
deterministic jitter using cursors. Now add
random jitter.
Demonstrate the use of
various "averaging" strategies to recover
the deterministic ISI-related jitter. Try
the vertical averaging mode on a scope. Also
try automated time-interval analysis.
Discuss the relation between the error
bounds on the computed answer and the number
of edges captured.
Point to remember:
Deterministic jitter has a well-defined
maximum worst-case peak value.
17. Extrapolation of
jitter probability distribution functions
Discuss how the random
component of jitter is extrapolated to
predict performance levels at very low BER.
The accuracy of the extrapolation depends on
the statistics of the jitter. It also
depends on the number of samples examined.
Derive error bounds for the extrapolated
data. Give advice on when and how
extrapolation techniques can be useful.
Point to remember:
The expected value of the worst-case peak
random jitter grows as a function of your
observation time. Most designers assume this
relationship is Gaussian.
18. Tracking down sources
of jitter
Present several
techniques to help you track down jitter
problems. Produce a serial datastream that
incorporates several sources of jitter. Show
several methods of quantifying the total
jitter. Demonstrate a method for eliminating
ISI, leaving only the remaining jitter
sources. Show how to quantify the impact of
switching power supply noise using a
correllation method. Try substituting a
quieter power supply. Track down
microphonics using a synchronous fan motor.
How to isolate your system from mechanical
noise. Discuss how the noise floor of your
instrument and the number of edges captured
affect the accuracy of your jitter
measurements.
Point to remember:
Careful sleuthing, and good test equipment,
is required to track down sources of jitter.
19. Separating random and
deterministic jitter
Set up a rotating machine
that exhibits both random and deterministic
jitter. From an opto-coupler, take a feed
off the main shaft to the oscilloscope, and
use that waveform as an example of a jittery
waveform. Illustrate simple deterministic
jitter (use a system of gears to enforce
variations at regular intervals). Also show
random jitter (jiggle the system
mechanically to introduce random
variations). Discuss methodologies to
separate the two.
Present the method of
harmonic analysis. Discuss the importance of
the jitter-filtering bandwidth of the
trigger circuit used to obtain the jitter
samples. Show how this work applies to the
separation of random and deterministic
jitter in serial-data waveforms.
Point to remember:
Deterministic jitter has an absolute
worst-case peak value, but random jitter
doesn't, which is why they are treated
separately in a good jitter budget.
20. Jitter budgets
Present a proto-typical
jitter budget for a serial-data transmission
system. Show how the budget is defined at
various points in a system, and how it
propagates deterministic and random jitter
separately. Make measurements to verify to
complicance of the system under test.
Point to remember:
It is posible, but by no means easy, to
verify the jitter budget in a high-speed
serial link.
21. Characterizing PCB
traces
Measuring DC resistance,
characteristic impedance, and high-frequency
line losses.
Design of test coupons.
Point to remember:
Good test coupons closely resemble the
worst-case traces of most concern.
22. Pre-emphasis and
equalization
Open with a general
discussion linear filtering using DSP
terminology (z-transforms).
Show an example of
pre-emphasis using a mechanical device. When
pulled by hand to the right, with point x
tracing a digital waveform, points y
and z-1y on the
stick trail the motion of the x
input. This operation synthesizes a simple
IIR low-pass filtering effect. When x
moves suddenly, it takes some time for y
to completely respond. Position a
woodworking router at point y and use
it to cut the track of y into a piece
of MDF. The track will show intersymbol
interference reminiscent of the way a long
transmission line distorts a serial-data
waveform.
Now insert pins in the
stick at positions z-1y
and y, and fit them into the y track.
When pulled along by hand to the right, the
tip of the stick (at x) perfectly
re-traces the original x waveform.
This operation constitues a form of
receive-based equalization.
The operations can be
reversed, first pre-emphasizing at the
transmitter and then passing through the
transmission-line filter, with the same
result. Discuss how noise is sometimes
amplified by an equalizer.
Show examples of simple
transmit-based and receive-based equalizers
used in actual products. Discuss the
implementation of more complex adaptive
equalization.
Point to remember:
Equalization is a powerful technique to
counteract ISI.
23. Adjustable drive
strength
Introduce the concept of
Zout for a driver. Show examples of how Zout
can be adjusted. Build circuits that benefit
from adjustable drive strength. Introduce
two main forms of response: the
"wimpy-driver" waveform that fails to meet
Voh (or Vol) on the first edge, and the
"ringing" waveform that overshoots and then
rings back on every edge. Diagnose a
waveform to determine whether the drive
strength is too great or too small.
Discuss why drive
strength in fast systems cannot be set by
resistors external to the driver package.
Point to remember:
One style of driver can't work in all
situations.
24. Ground bounce
Put a current clamp
around a BGA ball and measure the current.
This experiment will be conducted on a large
scale model of a BGA package. The setup
examines the effect of the number of ground
pins, and their placement. Advantages of
differential signaling are discussed.
Point to remember:
Power and ground BGA balls are just as
important as signal balls.
25. Power integrity
Discuss the purpose and
function of bypass capacitors. On-chip
bypassing is useful in certain
architectures, but not in others.
Bypassing is still needed for differential
systems. Present some of the data from Todd
Hubing's papers on the impedance of power
and ground planes. End with observations
about the importance of tight spacing
between the power and ground planes.
Point to remember:
Bypass capacitors exist to provide pathways
for returning signal current to hop between
power and ground nets.
26. Radiation
Discuss varous modes of
radiation, using the concept of "common-mode
current". Show direct radiation from a
heatsink. Show radiation from a microstrip
trace. Show radiation from a poorly-architected
pcb. Compare the forms of radiation to
determine which is most significant.
Point to remember:
Depending on your product architecture,
different forms of radiation dominate the
EMI signature.
27. Heatsinks
Conduct various
experiments with heatsinks, beginning by
cooking some eggs in a frying pan. Blow a
fan onto the frying pan and the eggs stop
cooking. Apparantly, airflow influences
temperature in a major way.
Show the heat-balance
equation for a heatsink. Couple a power-disspating
circuit to a waffle-style heatsink. Modulate
the amount of power dissipated and produce a
graph showing temperature versus power
dissipation. Make the same graph under
different conditions of airflow. Repeat the
experiment with the heatsink mouted inside a
small enclosed box. Conduct some
colored-smoke experiments to show "dead air"
patterns inside a typical product.
Conclude with advice
about the critical importance of providing
outside air circulation to heatsinks mounted
inside a product.
Point to remember:
Power dissipation times thermal resistance
equals the rise in temperature.
28. Time and frequency
Begin with an
audio-frequency demonstration showing how a
low-pass filter reduces high-frequency
content, rounding the waveform, and making
it sound "bassy".
Exploration of signals:
Investigate the correspondence between
risetime and bandwidth of a random digital
signal using both oscilloscope (time) and
spectrum analyzer (frequency) displays.
Adjust the rise time of the digital pulse
train to show the effect on the spectral
power density.
Exploration of linear
systems: Look at a poorly-terminated
transmission line using both time-domain and
frequency-domain views. Show the resonance
in the frequency domain (with network
analyzer). Show the step response (with TDT
measurement). Discuss the effect of the
risetime of the step used in this
measurement.
Combine the digital input
with the transmission-line system. The
shorter the risetime the higher the
bandwidth, and thus the greater the tendancy
of the un-terminated circuit to ring.
Point to remember:
Short scales of time correspond to high
frequencies.
29. BGA package
construction
Interview a package
fabrication expert on the subject of BGA
package construction. Show X-rays of ball
attachment. Show the manufacturing process.
Discuss the most common means of package
failure, including co-planarity soldering
failures. Explore the incredible array of
packaging diversity.
Point to remember:
BGA package performance affects your system
in a major way; it's worth keeping abreast
of the latest package design techniques.
30. SERDES performance
Determine how much power
supply noise the SERDES can tolerate without
violating its transmitted jitter
specification. Measure the power supply
noise in a typical digital product. Discuss
the means of designing and testing a power
supply filter to properly protect the power
input pin of the serializer.
Point to remember:
Power supply noise contributes as much or
more to jitter than anything else.
31. Single-ended via
optimization
Design and test several
layouts for single-ended stripline vias,
looking at through-performance, TDR, and
crosstalk.
Point to remember:
The layout of single-ended vias
significantly affects performance for
systems operating at 2.5 Gb/s and above.
32. Differential via
optimization
Design and test several
layouts for differential stripline vias,
looking at through-performance, TDR, and
crosstalk. Discuss "Coupling of Vias in
Electronic Packaging and Printed Circuit
Board Structures with Finite Ground Plane",
Leung Tsang and Dennis Miller, IEEE Trans.
Advanced Packaging, Nov. 2003, Vol. 26 #4,
page 375.
Point to remember:
The layout of differential vias
significantly affects performance for
systems operating at 2.5 Gb/s and above.
33. BGA breakout patterns
Layout a typical dog-leg
breakout pattern for a multilayer board
(single-ended signals). Measure the
crosstalk. Make TDR and TDT measurements.
Provide quantitative data showing the
importance of various layout features.
Point to remember:
The layout of BGA breakout patterns
significantly affects performance for
systems operating at 1 Gb/s and above.
34. Connector performance
Pick a backplane-style
connector. Measure the through performance.
Measure the crosstalk. Measure the ground
transfer impedance (for a differential
connector, this will have to do with the
common-mode content of the signals
conveyed).
Discuss the importance of
all three specifications in the context of
an overall link budget.
Point to remember:
The layout of via pads and clearances
underneath a high-speed connector
significantly affects its performance.
35. Via layout under
connector
Discussion of points
raised by James Clink in his paper to
DesignCon 2004 about BGA connectors. (1) The
patten of power and signal connections
influences crosstalk in a major way. (2) The
exact positioning of via locations
underneath the BGA doglegs matters. (3) The
assignment of which pins connect to which
layers can be optimized to minimize
crosstalk.
Point to remember:
The assignment of connectors pins to pcb
layers affects crosstalk.
36. Impact of holes in
power/ground planes
Measure the apparent
indutance of a ground plane as a function of
its physical size. Show the impact of holes
in the plane. Determine whether the holes
affect radiated emissions. Determine whether
large slots and gaps affect radiated
emissions. Demonstrate the advantage of
installing a solid metal pan adjacent to the
ground plane.
Point to remember:
Reference planes need not be solid, but they
must be fully interconnected to function.
37. Backplane
optimization
Introduce measures of
backplane performance. Present a typical
serial-data signal budget, and show which
factors are influenced by the backplane.
Discuss the influence of backplane
materials, connectors, and layout. Discuss
backplane density and layer count.
Especially consider the impact of layer
count on board thickness and therefore via
length.
Point to remember:
The design of a good backplane integrates
many conflicting requirements.
38. Surface-mounted
connectors: mechanical considerations
Begin by ripping a BGA
connector off of a pcb. Try another example
using a connector with feet that press or
solder into through-holes. Compare the
forces in the ripping experiments to the
forces encountered during card de-insertion.
Conclude that ripping the connector out of
the board during de-insertion is not a major
worry. Discuss what happens when the
backplane flexes during card INSERTION,
especially when a technician jams the card
home, concluding with advice about the
required mechanical stiffness of the
backplane to prevent failure during
insertion.
Compare the mechanical
problems with the signal quality advantages.
Point to remember:
BGA connectors can provide incredible signal
quality advantages.
39. Connector reliability
Interview a connector
designer about plating, corrosion, strength,
number of cycles, heat tolerance and other
mechanical issues. Show the manufacturing
process.
Point to remember:
The reliability of your whole system depends
on your connectors.
40. Meaning of IBIS
Premise: "Every design
group needs simulation software.". Use a
business analogy for managers:. "You can't
run the federal government without the OMB."
Show specific examples of
problems created by inadequate simulation
technology (i.e., crosstalk, ringing, and
overwhelming power supply noise). Discuss
the use of IBIS as a specification, not a
circuit emulator. Discuss the limits of
applicability for IBIS models. Relate this
whole discussion to the cost of product
design failure and the delay of new product
introduction.
Conclude with a
discussion of the general types of
simulation software necessary for high-speed
design work, and questions you can ask of
your engineers to make sure they are being
realistic in their requests for software.
Point to remember:
You can't make high-speed systems without
good simulation software.
41. Net topology I:
H-pattern distribution
Create an unterminated
H-pattern distribution topology for four
loads. Demonstrate the importance of
keeping the overall net delay small compared
to the signal risetime. Characterize the
H-pattern net in terms of the ratio of delay
to risetime. Show an improvement in
performance made possible by
series-terminating the driver. Show a
further improvement made possible by
sequencing the net impedance. Add capacitive
loads at the endpoints and show how things
get worse. Add unbalanced (max/min)
capacitive loades at the endpoints and show
how this creates new resonant modes. The
unbalanced (max/min) loading condition is a
worst-case condition for this style of net
and must always be included in the
acceptance test suite. Try various
additional features to combat the resonant
modes.
Point to remember:
The H distribution introduces almost no
skew, but is susceptible to resonance.
42. Net topology II:
Daisy chain
Create a daisy-chain
distribution topology for four loads.
Demonstrate the importance of keeping the
overall net delay small compared to the
signal risetime. Characterize the
daisy-chain net in terms of the ratio of
delay to risetime. Show an improvement in
performance made possible by
series-terminating the driver. Show a better
improvement in performance made possible by
end-terminating the net. Discuss the impact
of capacitive loading in the middle of a
transmission line.
Try various additional
features to combat the capacitive loading
(including necking down the trace width at
each load).
Point to remember:
A proper daisy chain delivers great signal
quality, but introduces skew.
43. Net topology III: Unterminated hairball networks
It's the ratio of
risetime to delay that matters. Generate
some random unterminated hairball
distribution topologies for four loads.
Demonstrate the importance of keeping the
overall net delay small compared to the
signal risetime. Stress each topology to
the limit at which it fails. Characterize
the hairball net in terms of the ratio of
delay to risetime. Show an improvement in
performance made possible by
series-terminating the driver. Show a
further improvement made possible by
sequencing the net impedance. Add capacitive
loads at the endpoints and show how things
get worse. Add unbalanced (max/min)
capacitive loades at the endpoints and show
how this creates new resonant modes. The
unbalanced (max/min) loading condition is a
worst-case condition for this style of net
and must always be included in the
acceptance test suite. Try various
additional features to combat the resonant
modes. Discuss the importance of testing
with worst-case min/max capacitances.
Point to remember:
You can make any hairball network function
if it's sufficiently short.
44. Net topology IV:
point-to-point
Create point-to-point
distribution topology for four loads.
Demonstrate the importance of keeping the
overall net delay small compared to the
signal risetime. Characterize the
point-to-point net in terms of the ratio of
delay to risetime. Show an improvement in
performance made possible by
series-terminating the driver. Add
capacitive loads at the endpoints and show
how this topology is relatively insensitive
to capacitive loading. Add unbalanced
(max/min) capacitive loades at the endpoints
and show how this creates timeing skew.
Review the properties of the H, Daisy-chain,
hairball, and point-to-point architectures.
Point to remember:
The point-to-point topology delivers the
best signal quality with fairly low skew,
but at a disadvantage in cost.
45. Simulation strategy
Some items you can
sucessfully simulate. Some items you can't.
Understanding the difference is the key to
project success. Discuss how to integrate a
simulation program with a test and
validation program. Whatever you do,
prepare an adequate budget for both time
and people involved in the simulation
process. Show project examples of what
simulation was performed when, how long it
took, and what were the overall results (Ed
Sayre, DDR-II).
Conclude with a
discussion of the benefits of a good
simulation program.
Point to remember:
Your simulation program must be integrated
with a test and validation program.
46. Optimize your layer
count
Begin with a discussion
of the impact of layer count on project
risk, and on production cost. An optimal
design process balances these two
considerations. The layer count influences
via length and trace width, which influence
signal propagation and crosstalk. The layer
count also affects power integrity. The
layer count has a major impact on production
cost. Show examples of boards made with
different tradeoffs in mind (NASA example).
Floorplanning must be undertaken with
crosstalk, signal loss, and power integrity
considerations in mind.
Point to remember:
Layer count significantly impacts both
signal quality, cost and design risk.
47. Logic families: SSTL
The SSTL standard allows
a certain reduction in signal amplitude.
This feature creates enormous flexibility in
routing and signal topology. Show the
traditional SSTL memory-interface topology,
and explain how it works. It is an example
of a design that, while far from optimal, is
"good enough". Show examples of optimal
serial-link topologies you can create with
SSTL. Demonstrate how SSTL, because of its
tight receiver thresholds, tolerates more
ISI than most other single-ended logic
families.
Point to remember:
Tight control over receiver thresholds
expands the range of applicability for any
logic family.
48. What's that glitch?
Certain circuit
topologies produce non-monotonic signal
behavior. Show examples of such topologies,
and help the viewer learn to instantly
recognize and diagnose these problems. Show
how adding capacitance to a node
sometimes identifies the source of a glitch.
Point to remember:
Non-monotonic glitches in signal waveforms
are usually caused by capacitive loading.
49. I'm not meeting V[OH]
Ten strategies for
dealing with wimpy drivers. (1) Budgeting
for more time-of-flight. (2) Doubling-up the
driver (not recommended). (3) Specifying a
better driver. (4) Reducing the load
capacitance. (5) Increasing the trace
impedance. (6) Reducing trace length. (7)
Reducing trace delay using a material with a
lower dielectric-constant. (8) Adjusting
split-end terminations. (9) Adding more
terminations rarely helps. (10) Using better
receivers.
Point to remember:
A wimpy driver can't deliver first-incident
wave switching on a long net.
50. My circuit rings
Circuits with powerful
drivers sometimes ring. These circuits
benefit from termination. Introduce
"lumped-element" analysis for understanding
ringing. Show the impact of increasing the
load capacitance. Strategies for dealing
with powerful drivers include: (1) Budgeting
for more time-of-flight. (2) Reducing the
load capacitance. (3) Reducing the trace
impedance. (4) Adding series terminations.
(5) Adding end terminations. (6) Adding a
resistor in the middle of the net. (7)
Adding diodes. (8) Adding an RC termination.
Point to remember:
An overly powerful driver benefits from any
form of damping.
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