High-Speed Digital Design Publications Archive by Keyword

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All Publications © by Dr. Howard Johnson 1993-2008 except as noted.

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Publications

attenuation	back plane	bandwidth	bypass capacitors
cables	characteristic impedance	chip packaging	clocks
connectors	crosstalk	data coding	delay
dielectric loss	differential signaling	dispersion	electromigration
EM fields	EMC	equalizer	Ernie
ESD	ferrite bead	Gigabit Ethernet	ground bounce
grounding	high-speed digital design formulas	hot plugging	interconnections
jitter	layer stack	layout	level translation
management	metastability	microstrip	multi drop
multi level	open drain	overshoot	PCI
power dissipation	power system	probes	proximity effect
reference plane	reflections	return current	ringing
rise time	sampled data	serial link	simulation
skew	skin effect	stripline	surface roughness
synchronization	system-on-a-chip	TEM mode	termination
testing	transmission line	via	wire wrap

attenuation,

and characteristic impedance, dispersion, transmission line

Lossless Propagation In the short term, the input impedance of a uniform, lossless, distortionless transmission line appears purely resistive. EDN 12/3/2007

and dielectric loss

Dielectric Loss Tangents For a capacitor formed from a lossy dielectric material, the loss tangent is the ratio at any particular frequency between the real and imaginary parts of the impedance of the capacitor. Newsletter v4-5 6/11/2001

and differential signaling, dispersion, serial link

Differential Receivers Tolerate High-Frequency Losses Differential receivers have more accurate switching thresholds than ordinary single-ended logic. EDN 11/28/2002

and management, serial link

Essential System Margin You should make tiny artificially adjustments to every line in the budget until you drive the system margin to zero. Only you will know where these adjustments are hidden. EDN 12/11/2003

and microstrip, skin effect

Passivation and Solder Mask Copper traces on outer layers must be protected from corrosion by passivation or by coating them with an inert material. EDN 6/13/2002

and serial link

Carrier Detection What happens when the opposing end of a link is disconnected, powered down, or disabled. EDN 9/4/2003

and skin effect

Nickel-Plated Traces We have been advised that due to the changes to the skin effect caused by the Ni/Au on the traces for high frequency RF designs we could be building in a problem. Newsletter v5-6 4/22/2002

and surface roughness, transmission line

Surface Roughness At a microscopic scale, no surface appears perfectly smooth. EDN 12/6/2001

and termination

Law of Product Development Regarding attenuating terminations, "The more independant requirements you place on a circuit, the more complex the circuit must become." Newsletter v8_06 10/3/2005

Voltage Conversion James Buchanon points out that my attenuating terminator may be impossible! Newsletter v9_01 1/4/2006

and testing

De-constructing Gain and Impedance from S11 From measurements of S11, determine both the gain and characteristic impedance of a uniform transmission structure. EDN 11/10/2005

back plane,

and bandwidth, testing

Frequent Obsession Frequency-domain instruments can play an important role in the measurement process, but should not be the main focus of your specification. EDN 10/12/2006

and crosstalk

Double-Tracking Let's begin this discussion looking at the belt-and-suspenders, super-safe differential stripline architecture. Newsletter v7_05 9/7/2004

and dielectric loss, via

Squeeze Your Layer Stack Given the same trace width and trace impedance, a lower dielectric constant lets you squeeze the layer stack. Newsletter v7_04 9/1/2004

and differential signaling, layer stack, serial link

Backplane Design Differential trace geometry, power and ground stackup for big backplane. EDN 5/25/2000

and multi drop, ringing

Bus Architecture and Timing The ratio (bus delay)/(clock period) is a key indicator of bus design difficulty. DesignCon 1999 1/30/1999

and multi level, serial link

Multi-Level Signaling -- Designcon2000 multi-amplitude signaling won’t help much below 2.5 Gb/s, however, at higher speeds where the loss slope increases MAS becomes very useful. DesignCon 2000 1/30/2000

and rise time, serial link

Millions and Billions When considering any aspect of your circuit geometry, the relation between physical size and risetime helps determine the relative importance of that object in the overall scheme of the circuit. EDN 8/18/2005

bandwidth,

Erroneous Harmonics You won't find a quote in my book about "harmonics" because that isn't a good way to look at the problem. Newsletter v4-9 10/4/2001

and back plane, testing

Frequent Obsession Frequency-domain instruments can play an important role in the measurement process, but should not be the main focus of your specification. EDN 10/12/2006

and delay, rise time, simulation, skin effect

Modeling Skin Effect Why does high-frequency current flow only on the outer surface of a printed-circuit trace? EDN 4/12/2001

and multi level, serial link

(The) Torches and the Hair Mankind has a long history of experience dealing with bandwidth-limited communication channels. DesignCon 2003 2/17/2003

and overshoot, TEM mode, transmission line

Strange Microstrip Modes "Quasistatic" values of capacitance and inductance are the values you get at low frequencies, near dc. EDN 4/26/2001

and reflections, ringing

Rising Problem The Gaussian edge best represents actual digital logic. It displays virtually no perceptible ringing in the time domain—just like the real circuit Newsletter v9_05 6/16/2006

and rise time, testing

Uncertainty Principle The shorter the duration of an event in time, the wider must be the spread of frequencies associated with it. EDN 7/19/2007

and testing

Pulse Width Compression A pulse-width compression test overcomes the limitations of probe placement and loading. EDN 3/29/2007

and transmission line

Transmission-line Scaling Every pc-board trace has a limited bandwidth. As chips go faster and faster, you eventually run into this limitation. EDN 2/4/1999

bypass capacitors,

Parasitic Inductance of Bypass II The following values for the inductance of a surface-mounted bypass capacitor were collected using the step-response technique described in chapter 8 of High-Speed Digital Design. Newsletter v6_09 12/1/2003

Quality Factor High-Q capacitors exacerbate resonances in a circuit, and resonance is the last thing you need in a power distribution system. Digital folks want low-Q capacitors. EDN 12/5/2005

and chip packaging, power system, termination

On-Chip Bypassing with Series Terminations On-chip capacitors perform brilliantly in a series-terminated architecture. EDN 4/29/2004

On-Chip Bypassing with End Terminations On-chip capacitors have no effect on single-ended systems with symmetrically-split end-terminations. EDN 5/27/2004

and layout

Operating Above Resonance It's OK to use a bypass capacitor well above its point of series-resonance. That's the normal mode of operation for most bypass capacitors. ED 4/14/1997

Bypass Arrays Does anyone out there actually DESIGN their bypassing networks? Newsletter v1-6 7/25/1997

Capacitor Placement The function of a bypass capacitor is this: to help returning signal current get from the board back into the driver. Newsletter v2-1 1/7/1998

Bypass Capacitor Layout Little traces between your bypass capacitors and the power planes have a big effect on performance. Newsletter v2-3 1/23/1998

(The) Way Home Current always makes a loop. If it goes out, it must find a way back home. The shapes of both the outgoing and the return paths affect the observed inductance. EDN 6/22/2000

Parasitic Inductance of Bypass Capacitors You can estimate the parasitic series inductance of a bypass capacitor in a multi-layer board with solid power and ground planes. EDN 7/20/2000

Bypass Capacitor Sequencing A trace of any practical length placed in series with the power terminal of a high-speed IC (especially one with multiple VCC pins) radically increases power supply noise at the VCC terminal and should be avoided like the plague. Newsletter 9_07 10/4/2006

and layout, power system

Bypass Capacitor Layout The primary symptoms of an inadequate, old-fashioned bypass capacitor array are increased power supply noise, increased crosstalk among signal traces, and increased electro-magnetic radiation. PCD 8/1/1997

Capacitor Layout Matters Your problem is likely caused by the layout, which has more than tripled the inductance of each bypass capacitor, not the values of types of capacitance. EDN 9/5/2002

and management, power system

ESR of Regulator Output Capacitor How can the ESR of a bulk capacitor (tantalum or electrolytic capacitor) affect a linear voltage regulator? Newsletter v5-3 2/25/2002

and power system

Bypass Multi-Valued Arrays I discourage engineers from combining together different-valued capacitors if they share the same package format. Newsletter v1-17 11/14/1997

Bypass Capacitor Array This spreadsheet produces a beautiful color version of my figure 8.9 showing the impedance of each element of a power system and also the composite impedance of all four elements taken in parallel. Newsletter v6-02 1/24/2003

Voltage Regulator Model One step-response test reveals enough information to form a simple circuit model of most any voltage regulator. EDN 8/17/2006

VRM Stability - Part II: ESR The ESR of your VRM output capacitor controls both its ripple amplitude and stability. Newsletter v10_4 9/17/2007

cables,

Why 50-Ohms Mailbag Regarding my article "Why 50 Ohms?" (EDN, Sept 14, 2000, pg 30), I received some interesting justifications for the use of 50-ohm coaxial cabling. EDN 1/4/2001

and connectors, EMC, ground bounce

Signal Ground Drain Wire Why should disconnecting the "drain wire" at the connectors have such a drastic impact on the rise/fall time of the outer conductors? Newsletter v2-32 12/4/1998

and connectors, EMC, grounding

Cable Shield Grounding Joe, I am going to disagree with your suggestion that a shield with a resistor at one end acts as an effective EMI shield. In high-speed digital applications, it doesn't. Newsletter v2-2 1/16/1998

and differential signaling

Ribbon Cable Impedance The impedance of flat-ribbon cable depends on the pattern of grounds. Newsletter v3-10 4/6/1999

and equalizer

Equalizing Cables How do you equalize LVDS signals transmitted through cables of say 10 to 50m? EDN 8/2/2001

and layout, reflections, termination

Matching Pads The only passive circuits that guarantee good impedance translation for wideband signals are resistive pads. EDN 12/21/2000

and rise time

Risetime of Lossy Transmission Line The risetime of a long skin-effect limited cable scales with the square of its length, not according to the sum-of-squares rule for [the risetime of] cascaded linear systems. EDN 10/2/2003

and transmission line

Why 50 Ohms? Why do most engineers use 50-ohm pc-board transmission lines? Why not 60 or 70 ohms ? EDN 9/14/2000

So Good it Works on Barbed Wire Next time you look at a transmission line, I hope you'll focus on the big four properties: characteristic impedance, high-frequency loss, delay, and crosstalk. EDN 7/5/2001

characteristic impedance,

and attenuation, dispersion, transmission line

Lossless Propagation In the short term, the input impedance of a uniform, lossless, distortionless transmission line appears purely resistive. EDN 12/3/2007

and connectors

Tapered Transitions Consider the problem of adapting a straddle-mount SMA connector for a 10-Gbps digital application. EDN 10/11/2001

and crosstalk, jitter

Memory Bus Crosstalk I am currently working on high speed memory bus with “interconnect jitter”. My memory recommends changing the bus geometry to improve timing. Newsletter v9_06 8/22/2006

and dielectric loss, skin effect

Characteristic impedance of lossy line Skin-effect losses increase the real part of the impedance curve in the vicinity of the skin-effect onset, while the dielectric losses decrease the real part of impedance in the same area. EDN 10/3/2002

and differential signaling

Differential (Microstrip) Trace Impedance Many different combinations of height, width and spacing can generate the same differential impedance. Newsletter v5-2 1/22/2002

Reference-Free Pair An "image plane" method calculates the impedance of an over/under configuration with no solid reference plane. EDN 7/20/2006

and reflections, transmission line

A transmission line is always a transmission line Does the input impedance behave one way on a long transmission line but differently when the load is adjacent to the driver? How does it know what to do? EDN 4/4/2002

and testing

See Beyond the Edge The far-end reflected signal is usually considered the end of usable data in a TDR waveform, but a wealth of information lies beyond this point. EDN 10/13/2005

chip packaging,

10 Reasons Why I Love the BGA Ball Grid Array (BGA) packages are taking the industry by storm, and I’m glad to see it. ED 3/17/1997

I Still Love the BGA Hate mail, mostly from mechanical designers and production test engineers, about BGA's Newsletter v2-10 4/6/1998

and bypass capacitors, power system, termination

On-Chip Bypassing with Series Terminations On-chip capacitors perform brilliantly in a series-terminated architecture. EDN 4/29/2004

On-Chip Bypassing with End Terminations On-chip capacitors have no effect on single-ended systems with symmetrically-split end-terminations. EDN 5/27/2004

and connectors

Straddle-Mount Connectors Follow-up to "Tapered Transitions", EDN 11 Oct., 2001 Newsletter v4-18 12/19/2001

and differential signaling, ground bounce

A Time for All Things There is a good time and a bad time for a chip to sample its digital inputs. EDN 6/21/2001

and EM fields, rise time

Think Small The three-dimensional rule for physical scaling of electrical connections immutably controls the performance of connectors, packages, component bodies, vias, and many other common structures. Newsletter v8_04 5/4/2005

and EMC

Submicron ASICs and EMI-EMC Above Fk the limited rise/fall time in your chips provides a natural filtering effect that limits emissions. EDN 4/13/2000

clocks,

and delay, skew

Serpentine Delays If you are using some form of delay line to match clock delays at all points of usage within a pc board, here's a short list of the items you need to match: EDN 2/15/2001

Negative Delay If Congress invented negative-delay legislation, it might improve its reputation for alacrity. EDN 8/30/2001

and differential signaling

Differential Clocks What's the impact of using differential clocks in a parallel bus? Newsletter v1-10 9/4/1997

and EMC, jitter

Intentional Clock Modulation Over the years, various techniques have been proposed for modulating, or dithering, the clock frequency to break up the accumulated spectral power into a larger number of new modes. EDN 8/3/1998

Signal Integrity Mailbag My recent column on intentional clock modulation (EDN, Aug 3, 1998, pg 24) spurred some interesting responses from readers. EDN 10/8/1998

Jitter-Free Clocks Is there any way to make a timing reference that has low jitter and low spectral peaks and at the same time is compatible with zero-delay-repeater structures? EDN 8/5/1999

and interconnections, level translation

When to use AC Coupling When should one adopt DC coupling versus AC coupling? Newsletter v4_15 11/13/2001

and jitter

(The) Jitters If you are using a clock multiplier, or a PLL-based clock regenerator, make sure to comply with the specifications for offset, wander, and jitter on the reference clock input. ED 1/20/1997

Jitter and Phase Noise Converting spectral-power-density noise measurements into rms and peak-to-peak jitter. Newsletter v4-7 6/25/2001

Random and Deterministic Jitter The point of separating jitter into random and deterministic components is that the deterministic components have a lower ratio of peak value to standard deviation than do the random components. EDN 6/27/2002

Clock Jitter Propagation Any sort of resonance, even a tiny one, spells disaster for a highly cascaded system. EDN 2/6/2003

Jitter and SNR Combined I would rather not consider of the joint probability of occurrence of vertical noise and horizontal jitter in the same equation. Newsletter v7_06 11/18/2004

and overshoot, skew

Intentional Overshoot Ernie reduces the value of his series terminator, inducing some intentional overshoot that partially compensates for the lack of vivre in the received signal and speeding up (slightly) the threshold crossing. EDN 8/7/2003

and skew

Tips on Controlling Clock Skew Your ability to manage and control clock skew has been recently improved by the introduction of a new generation of multi-output, low-skew clock drivers. ED 7/21/1997

and skew, synchronization

Synchronizing clocks What should I do to prevent noise problems if I choose not to synchronize the whole clock tree. Newsletter v4-6 6/19/2001

connectors,

and cables, EMC, ground bounce

Signal Ground Drain Wire Why should disconnecting the "drain wire" at the connectors have such a drastic impact on the rise/fall time of the outer conductors? Newsletter v2-32 12/4/1998

and cables, EMC, grounding

and characteristic impedance

Tapered Transitions Consider the problem of adapting a straddle-mount SMA connector for a 10-Gbps digital application. EDN 10/11/2001

and chip packaging

Straddle-Mount Connectors Follow-up to "Tapered Transitions", EDN 11 Oct., 2001 Newsletter v4-18 12/19/2001

and crosstalk

Mutual Understanding A connector configured with too few power and ground pins, or with too many heavy loads, generates a lot of crosstalk. EDN 1/1/1998

and crosstalk, Ernie

Through-hole Clearances Connectors require continuity of the ground plane underneath the connector. EDN 7/8/1999

and crosstalk, layer stack, via

Connecting Layers In a multi-layer pcb the vias perform the role of a tiny connector, where the signal-to-ground-via ratio controls via crosstalk. EDN 7/22/2004

and crosstalk, multi level

Shannon Says Connector vendors will soon realize that great improvements in the information-carrying capacity of their products may be had by reducing crosstalk. EDN 11/13/2003

and crosstalk, testing

Measuring Connectors I would like to replace one connector type with a different, less expensive model. How do I prove the two connectors have the same electrical characteristics? EDN 5/10/2001

and differential signaling, stripline

Differential U-Turn What is the effect of a split in a solid plane on the impedance of a coplanar differential pair? EDN 9/1/2000

and probes, testing

Step Response Test My favorite repetitive step response stimulus is a simple square wave with 50% duty cycle. (This article includes many details of measurement technique and interpretation.) Newsletter v11_01 3/13/2008

Confirm the Diagnosis The confirmation step is crucial because it takes a lot of time to do re-work, or re-layout, and you must be sure of your conclusions (3.125 Gb/s serial link). Newsletter v11_02 3/26/2008

crosstalk,

Software Crosstalk Explains why software tests for ringing and crosstalk are necessary and what specific features are needed. Newsletter v5-0 6/24/2002

Acceptable Crosstalk What is the limit of crosstalk that can be ignored? (and frozen turkeys) Newsletter v5-11 10/30/2002

and back plane

Double-Tracking Let's begin this discussion looking at the belt-and-suspenders, super-safe differential stripline architecture. Newsletter v7_05 9/7/2004

and characteristic impedance, jitter

Memory Bus Crosstalk I am currently working on high speed memory bus with “interconnect jitter”. My memory recommends changing the bus geometry to improve timing. Newsletter v9_06 8/22/2006

and connectors

Mutual Understanding A connector configured with too few power and ground pins, or with too many heavy loads, generates a lot of crosstalk. EDN 1/1/1998

and connectors, Ernie

Through-hole Clearances Connectors require continuity of the ground plane underneath the connector. EDN 7/8/1999

and connectors, layer stack, via

Connecting Layers In a multi-layer pcb the vias perform the role of a tiny connector, where the signal-to-ground-via ratio controls via crosstalk. EDN 7/22/2004

and connectors, multi level

Shannon Says Connector vendors will soon realize that great improvements in the information-carrying capacity of their products may be had by reducing crosstalk. EDN 11/13/2003

and connectors, testing

Measuring Connectors I would like to replace one connector type with a different, less expensive model. How do I prove the two connectors have the same electrical characteristics? EDN 5/10/2001

and differential signaling

Differential Crosstalk I have a number of high-speed differential PECL signals that I need to route in parallel on the PCB. Newsletter v3-20 8/23/1999

and differential signaling, layout

Mitigating Crosstalk What can be done to reduce the amount of crosstalk in a pcb. Newsletter v6-01 1/20/2003

and EMC

Noise Partitioning (by W. Michael King) Keep your loud, high-powered partitions from interfering with your little-bitty quiet ones. EDN 3/4/2004

and ferrite bead

Using Ferrites If two or more ferrites are placed parallel and close to each other will this result in crosstalk between them? Newsletter v1-2 6/13/1997

and ground bounce

Crosstalk and SSO Noise What you need is a simple experiment that will separate the effects of SSN (simultaneous switching noise) from other crosstalk. Newsletter v3-9 3/30/1999

BGA Crosstalk Details, measured lab results, and theory of crosstalk involving hundreds of outputs switching simultaneously in a high-speed Xilinx Virtex-4 FPGA package, as delivered to the Xilinx tech on-line forum March 1, 2005. Newsletter v8_03 3/1/2005

Spread Your Returns BGA package analysis; Signals closest to a good return suffer the least ground bounce. EDN 3/31/2005

Big Buffer Do you suppose there is much SSO noise margin left in a typical IC package design? Can you safely exceed the loading guidelines without causing SSO errors? I doubt it. Newsletter v8_07 10/18/2005

and grounding

Reason for Ground Split There are indeed applications so sensitive that they require separation of the analog and digital ground regions. Newsletter v9_04 3/24/2006

and grounding, reference plane

Noise Isolation Achieving isolation greater than 80 dB. Newsletter v2-13 5/19/1998

and high-speed digital design formulas, proximity effect, return current

Proximity Effect III Justification for crosstalk approximation (see High-Speed Digital Design p. 190, eqn. [5.1]) Newsletter v4-8 10/3/2001

and layout

Directionality of Crosstalk (Originally titled: The Real Truth About Crosstalk) If you are trying to manage crosstalk from first principles, so it comes out right on the first spin, look into the new crosstalk prediction tools that feature IBIS I/O modeling. ED 8/18/1997

(The) Real Truth About Crosstalk If you are trying to manage crosstalk from first principles, so it comes out right on the first spin, look into the new crosstalk prediction tools that feature IBIS I/O modeling. ED 8/18/1997

Trace Between Capacitors Will crosstalk occur if I route a trace underneath a bypass capacitor? Newsletter v3-4 1/28/1999

Crosstalk at Right Angles Crosstalk for traces crossing at right angles. Newsletter v3-6 2/26/1999

and management, testing

Margin Testing (by JP Miller) Testing a link in isolation is never sufficient; links must be tested in combination with other noise sources. EDN 3/3/2005

and power system

VRM Stability - Part I: Feedback Feedback must be carefully controlled because, by its very nature, feedback invites the risk of self- oscillation. Newsletter v10_3 9/10/2007

and via

Crosstalk - Via to Trace Measurements of crosstalk between an interplane via and an inner-layer trace relevant to the question of minimum separation between a sensitive differential analog pair and a digital via on the same PCB. Newsletter v8_01 1/25/2005

Crosstalk - Differential Vias My CAD tools predict the level of crosstalk from differential digital traces to differential analog traces. That's fine, but how about the crosstalk from differential digital vias to differential analog vias? How does that work and how big is it? Newsletter v8_02 2/15/2005

Crosstalk - Differential Vias with Grounds Ground vias, used in conjunction with a differential pair, arrest the spread of crosstalk. EDN 4/28/2005

data coding,

Killer Packet Scrambling by itself does *nothing* to improve the worst case DC balance. Newsletter v5-7 6/7/2002

and EMC

Scrambled Bus The improvement in common-mode radiation from the straight, unencoded, worst-case example to the best scrambled-and-coded version is better than 30 dB. Newsletter v7_10 12/14/2004

and Gigabit Ethernet

Fiber-Optic Encoding Codes that scramble the data post-coding cannot control either the DC balance or the maximum run-length of the scrambled output. EDN 1/10/2002

and ground bounce

Data Coding for Low Noise Limited-weight codes provide noise-canceling properties similar to differential signaling, but using fewer interconnections. EDN 6/24/2004

and layout, reflections

AC Coupling Layout (for XAUI 3.125 Gb/s) The parasitic body capacitance of the AC coupling caps perturbs the characteristic impedance of your transmission line. Newsletter v10_02 5/18/2007

and level translation

SONET data coding Figure 1 shows one way to build a non-linear DC restorer. This circuit fixes the DC balance of a SONET data string that has lost its DC level because of AC-coupling. Newsletter v5-5 3/29/2002

and level translation, reflections, serial link

DC Blocking Capacitor Placement Slower systems sometimes benefit from placing the DC blocking capacitors close to the source, but not multi-gigabit systems. Newsletter v7_08 12/12/2004

DC Blocking Capacitor Value How do I choose the value for a DC blocking capacitor in a serial link application? Newsletter v7_09 1/10/2005

and serial link

Serial Killers If you are responsible for selecting a serial interface standard, I'd like to pass along a few ideas for your selection criteria, starting with some concepts having to do with the physical link protocol, particularly DC balance. Newsletter v7_07 12/1/2004

delay,

Settling Time Measurements What is the correct method to measure the settling time of a digital waveform? Newsletter v3-17 7/28/1999

and bandwidth, rise time, simulation, skin effect

Modeling Skin Effect Why does high-frequency current flow only on the outer surface of a printed-circuit trace? EDN 4/12/2001

and clocks, skew

Serpentine Delays If you are using some form of delay line to match clock delays at all points of usage within a pc board, here's a short list of the items you need to match: EDN 2/15/2001

Negative Delay If Congress invented negative-delay legislation, it might improve its reputation for alacrity. EDN 8/30/2001

and multi drop, PCI

PCI Series Terminations Resistors It's OK to use series termination resistors with bi-directional transceivers. The series resistor just delays the incoming signals and degrades their risetimes. Newsletter v1-4 7/4/1997

and testing

Finger the Culprit When debugging a rare mode of failure, never attempt a direct fix. The test cycles associated with each attempted improvement will kill your development schedule. Your first order of business is to make the problem worse. EDN 6/21/2007

and transmission line

Slow Wave Mode The slow-wave effect hampers signal transmission on some on-chip MIS (metal-insulator-semiconductor) interconnections. EDN 11/8/2001

and via

Delay Through Via For vias which traverse several planes, the delay is a function not only of the via but also of the position and configuration of nearby bypass capacitors. Newsletter v2-29 10/29/1998

dielectric loss,

and attenuation

and back plane, via

Squeeze Your Layer Stack Given the same trace width and trace impedance, a lower dielectric constant lets you squeeze the layer stack. Newsletter v7_04 9/1/2004

and characteristic impedance, skin effect

and dispersion, skin effect

Mixtures of skin-effect and dielectric loss Long, high-speed pcb traces operate in a zone influenced by both skin-effect and dielectric losses. Both mechanisms attenuate the high-frequency portion of your signals, but in slightly different ways. EDN 9/19/2002

differential signaling,

Differential Signaling (Through Connectors) I have 16 differential line pairs that have to go through a connector. What signal to ground ratio and pattern should I use? Newsletter v3-12 5/7/1999

and attenuation, dispersion, serial link

Differential Receivers Tolerate High-Frequency Losses Differential receivers have more accurate switching thresholds than ordinary single-ended logic. EDN 11/28/2002

and back plane, layer stack, serial link

Backplane Design Differential trace geometry, power and ground stackup for big backplane. EDN 5/25/2000

and cables

Ribbon Cable Impedance The impedance of flat-ribbon cable depends on the pattern of grounds. Newsletter v3-10 4/6/1999

and characteristic impedance

Differential (Microstrip) Trace Impedance Many different combinations of height, width and spacing can generate the same differential impedance. Newsletter v5-2 1/22/2002

Reference-Free Pair An "image plane" method calculates the impedance of an over/under configuration with no solid reference plane. EDN 7/20/2006

and chip packaging, ground bounce

A Time for All Things There is a good time and a bad time for a chip to sample its digital inputs. EDN 6/21/2001

and clocks

Differential Clocks What's the impact of using differential clocks in a parallel bus? Newsletter v1-10 9/4/1997

and connectors, stripline

Differential U-Turn What is the effect of a split in a solid plane on the impedance of a coplanar differential pair? EDN 9/1/2000

and crosstalk

Differential Crosstalk I have a number of high-speed differential PECL signals that I need to route in parallel on the PCB. Newsletter v3-20 8/23/1999

and crosstalk, layout

Mitigating Crosstalk What can be done to reduce the amount of crosstalk in a pcb. Newsletter v6-01 1/20/2003

and EMC

Differential-to-common-mode conversion Any imbalanced circuit element within an otherwise well-balanced transmission channel creates a region of partial coupling between the differential and common modes of transmission at that point. EDN 10/17/2002

Reducing EMI with Differential Signaling You need not struggle to place ordinary differential digital traces any closer than 0.5 mm for any EMI purpose. EDN 12/12/2002

and EMC, skew

Common Mode Analysis of Skew A twenty-percent skew creates a ten-percent common-mode component. EDN 1/22/2004

and layer stack, layout, skew

Asymmetry in Broadside Configuration In general I avoid broadside-coupled traces unless they are made necessary by routing considerations. EDN 11/14/2002

and layout

Differential Routing Is it better to route differential traces over/under (broadside) or side-by-side (edge-coupled)? Newsletter v2- 30 11/11/1998

and probes, testing

Differential TDR A differential TDR instrument provides two outputs, x and -x, which you connect to the traces under test. EDN 8/22/2002

and reflections, transmission line

Differential Reflections Does the standard formula for reflections also apply to differential/balanced lines where two lines carry one signal? Newsletter v2-21 8/17/1998

and return current

Return Current Matters Differential architectures sometimes tempt us to ignore return current issues… [but] even in a differential configuration, current flows on the planes under each trace separately. EDN 9/16/2004

and skew

Differential Pair Skew What impact does pair skew have on a received differential signal? Newsletter v1-7 8/5/1997

Your layout is skewed Chamfering or rounding of differential corners does not eliminate skew. EDN 4/18/2002

Buying Time Two strategies for minimizing the intra-pair skew accumulated by a differential net: (1) A pair that starts and ends going north has by definition equal numbers of right and left-hand turns. (2) How your layout enters or leaves a BGA makes a difference. EDN 5/2/2002

Slippery Slopes Differential Skew revisited -- skew disperses your risetime, increasing your susceptibility to jitter caused by additive noise EDN 4/1/2004

and termination

PECL Biasing I thought that PECL outputs always need external resistors to ground since PECL drivers can only source current but not sink it. Newsletter v1-5 7/14/1997

Differential Termination Terrible things can happen to the common-mode artifacts if your trace delay equals one-quarter of the clock period. EDN 6/8/2000

dispersion,

and attenuation, characteristic impedance, transmission line

Lossless Propagation In the short term, the input impedance of a uniform, lossless, distortionless transmission line appears purely resistive. EDN 12/3/2007

and attenuation, differential signaling, serial link

Differential Receivers Tolerate High-Frequency Losses Differential receivers have more accurate switching thresholds than ordinary single-ended logic. EDN 11/28/2002

and dielectric loss, skin effect

and microstrip, transmission line

Strange Microstrip Mailbag Follow-up to April 26, 2001 column in EDN, “Strange Microstrip Modes. Newsletter v4-16 11/28/2001

electromigration,

and ESD, overshoot, ringing

(For Your) Protection Protection diodes have a limited lifetime—don't wear them out. EDN 12/9/2004

and management, power dissipation

Relevance of Physics The engineering curriculum for first-year students at Oxford University still includes a good amount of basic physics—despite attempts by computer scientists at some universities to de-emphasize that subject. EDN 5/1/2003

EM fields,

and chip packaging, rise time

and high-speed digital design formulas, return current, via

Via Inductance The inductance of a via depends on the path of returning signal current. Newsletter v6-04 3/15/2003

and power system, return current, via

Short-Term Impedance of Planes Doesn't the returning signal current just pop between the planes through the parasitic capacitance of the planes themselves, you might ask? Newsletter v6_05 3/24/2003

and return current

Minimum-Inductance Distribution of Current Faraday, in his mind's eye, saw lines of force traversing all space. Newsletter v6_07 7/22/2003

and via

In-Between Spaces According to Kirchoff's laws for circuit analysis, the total inductance of two inductors placed in series should equal the sum of their independent inductances -- not true for high-speed digital circuits. EDN 5/24/2007

EMC,

Why Digital Engineers Don't Believe in EMC Digital engineers don't believe current flows in loops, existence of the H-field, gates are differential amplifiers, existence of EM waves, or that EMC will advance their careers EMC Soc nwsltr 3/2/1998

Going Vertical Keeping your traces close to a solid, uninterrupted reference plane is one of simplest, most effective things you can do to reduce electromagnetic radiation and harden your product against ESD. EDN 10/14/1999

Musical Interference When you can walk up to your equipment and make it play Dixie on an AM radio, you will have captured the attention of your digital engineers. EMC Soc Nwsltr 7/1/2002

Working with EMC Consultants The biggest EMC mistake you can make is the failure to get your consultant involved at a sufficiently early stage. Newsletter v5-10 9/10/2002

and cables, connectors, ground bounce

Signal Ground Drain Wire Why should disconnecting the "drain wire" at the connectors have such a drastic impact on the rise/fall time of the outer conductors? Newsletter v2-32 12/4/1998

and cables, connectors, grounding

and chip packaging

Submicron ASICs and EMI-EMC Above Fk the limited rise/fall time in your chips provides a natural filtering effect that limits emissions. EDN 4/13/2000

and clocks, jitter

Signal Integrity Mailbag My recent column on intentional clock modulation (EDN, Aug 3, 1998, pg 24) spurred some interesting responses from readers. EDN 10/8/1998

Jitter-Free Clocks Is there any way to make a timing reference that has low jitter and low spectral peaks and at the same time is compatible with zero-delay-repeater structures? EDN 8/5/1999

and crosstalk

Noise Partitioning (by W. Michael King) Keep your loud, high-powered partitions from interfering with your little-bitty quiet ones. EDN 3/4/2004

and data coding

Scrambled Bus The improvement in common-mode radiation from the straight, unencoded, worst-case example to the best scrambled-and-coded version is better than 30 dB. Newsletter v7_10 12/14/2004

and differential signaling

Reducing EMI with Differential Signaling You need not struggle to place ordinary differential digital traces any closer than 0.5 mm for any EMI purpose. EDN 12/12/2002

and differential signaling, skew

Common Mode Analysis of Skew A twenty-percent skew creates a ten-percent common-mode component. EDN 1/22/2004

and ferrite bead, power system

Segmenting the Vcc Plane I don't cut up the Vcc plane unless I have one circuit that is substantially more sensitive to Vcc noise than the other circuits on the board. Newsletter v2-18 7/23/1998

and grounding

Moats and Floats How to conduct multiple comparative layout studies in one pcb fabrication cycle. ED 2/17/1997

Picket Fences (by W. Michael King) About the use of a "picket fence" array of ground vias to shield internal sections of a board from each other. Newsletter v2-16 6/8/1998

Radiated Digital Ground Noise Ideally, you should ground your digital logic, the chassis, any cable grounds, and the cable shield (if present) to a common point. Newsletter v2-17 6/26/1998

Hidden Schematic (by Bruce Archambeault) Dr. Bruce Archambeault, creator of the IBM EMC rule-checking program "EMSAT", says "Ground is a good place to grow potatoes and carrots", but a poor concept for high-frequency engineering. EDN 5/25/2006

and grounding, power system

Front-Connected Power Supply Why connections on the front side of a plug-in card are a bad idea. Newsletter v4-17 12/5/2001

and grounding, reference plane

Ground Fills The "poured ground" (more commonly called a "ground fill") is a technique useful on two-layer boards for reducing crosstalk due to ELECTRIC FIELD coupling. Superceded by "Ground Fill", EDN 26 May 2005. -- Orig. pub: Newsletter v1-3 6/24/1997

Ground Fill Isolated, discontinuous regions of ground fill do not help reduce magnetic-field coupling between traces or radiation from the board. EDN 5/26/2005

and management

Not all EMC engineers are bald If you want to keep doing what you love to do you must constantly re-educate yourself. EDN 1/24/2002

and simulation

Simulation Software What are the primary issues at hand, and what are the important questions to ask before you get yourself mired in a project that may not pay off. Newsletter v1-16 11/4/1997

EMI Simulations Tools (Originally titled: EMI Simulation Tools) Many EMI simulators are embellished with flashy demonstrations, which, like the smell of coffee brewing, or the sound of bacon frying, promise more than they can possibly deliver. EDN 3/2/1998

and termination

Reducing Emissions (by Bruce Archambeault) Most radiated emissions problems depend more on signal currents than signal voltages. The source-termination resistance controls both received signal amplitude and drive current. EDN 3/1/2001

Value of End Terminator Should an end-terminator always be set at the highest value that works because that minimizes the current and therefore gives the best EMI performance? Newsletter v5-1 1/7/2002

equalizer,

and cables

Equalizing Cables How do you equalize LVDS signals transmitted through cables of say 10 to 50m? EDN 8/2/2001

and reflections, termination

Constant-Resistance Equalizer This circuit combines a good termination with a useful equalizing function. EDN 7/10/2003

Ernie,

and connectors, crosstalk

Through-hole Clearances Connectors require continuity of the ground plane underneath the connector. EDN 7/8/1999

and management

Ernie's Story Engineers without a basic understanding of high-speed effects will likely end up just like Ernie, sitting in somebody else's office, fidgeting and sweating. ED 12/1/1996

and power system

Healthy Power When your prototype board comes back from fabrication, take the time to check the health of its power system. EDN 3/30/2000

ESD,

Watery Grave Design your system to survive near-miss situations. The most common near-miss scenarios include discharges to your product chassis, the wires leading into or out of your chassis, or metallic objects near those wires. EDN 6/23/2005

and electromigration, overshoot, ringing

(For Your) Protection Protection diodes have a limited lifetime—don't wear them out. EDN 12/9/2004

and testing

Nasty ESD Testing A thin, plastic package sitting on a metal desk, with wires hanging out the back of the package will prove embarrassingly susceptible to ESD. Newsletter v4-13 10/24/2001

ferrite bead,

Ferrite Beads Ferrite beads come in two flavors: high-Q, resonant beads and low-Q, non-resonant beads, also called lossy, or absorptive beads. EDN 10/12/2000

and crosstalk

Using Ferrites If two or more ferrites are placed parallel and close to each other will this result in crosstalk between them? Newsletter v1-2 6/13/1997

and EMC, power system

Segmenting the Vcc Plane I don't cut up the Vcc plane unless I have one circuit that is substantially more sensitive to Vcc noise than the other circuits on the board. Newsletter v2-18 7/23/1998

and probes

Probing Two Points You should ground each probe near its respective point of measurement. Newsletter v5-12 9/18/2002

Gigabit Ethernet,

Gigabit Ethernet Gigabit Ethernet is going to be faster, with more parallel signals, and tighter layout constraints. PCD 2/1/1997

Setting the Standard for Gigabit Ethernet The Gigabit Ethernet standard provides for a number of physical layer transmission interfaces. ED 6/23/1997

Driving the World of Gigabit Ethernet How should we best specify the I/O performance of drivers for the Gigabit Ethernet parallel interface? EDN 11/6/1997

Gigabit Ethernet Specification The GMII is designed as a chip-to-chip interface. The expected link distance is therefore about 3 to 12 inches. Newsletter v2-6 2/2/1998

and data coding

Fiber-Optic Encoding Codes that scramble the data post-coding cannot control either the DC balance or the maximum run-length of the scrambled output. EDN 1/10/2002

ground bounce,

and cables, connectors, EMC

Signal Ground Drain Wire Why should disconnecting the "drain wire" at the connectors have such a drastic impact on the rise/fall time of the outer conductors? Newsletter v2-32 12/4/1998

and chip packaging, differential signaling

A Time for All Things There is a good time and a bad time for a chip to sample its digital inputs. EDN 6/21/2001

and crosstalk

Crosstalk and SSO Noise What you need is a simple experiment that will separate the effects of SSN (simultaneous switching noise) from other crosstalk. Newsletter v3-9 3/30/1999

Spread Your Returns BGA package analysis; Signals closest to a good return suffer the least ground bounce. EDN 3/31/2005

and data coding

Data Coding for Low Noise Limited-weight codes provide noise-canceling properties similar to differential signaling, but using fewer interconnections. EDN 6/24/2004

and level translation, rise time

Asymmetric Noise Margins Extreme asymmetries in the noise margin budget for a logic family create a preferred logic level. EDN 3/15/2001

grounding,

Earth Ground The most important point to make with regard to grounding is that the input to every digital logic gate is a DIFFERENTIAL amplifier. Newsletter v2-12 5/7/1998

Single Point Ground Moat-and-drawbridge approach used on mixed-signal board. Newsletter v2-26 9/29/1998

ADC grounding Chip designers often internally partition the ground-reference net (or substrate) for an ADC into isolated analog and digital regions. EDN 12/7/2000

Multiple ADC grounding Several of you wrote about "ADC Grounding" (EDN, Dec 7, 2000, pg 36) to ask what happens when you have more than one ADC. EDN 2/1/2001

Common-mode ground currents Instead of thinking of your digital ground region as a solid sheet, think of it as a picture frame. This simple model explains the basis of single-point grounding and many other common-mode noise issues. Newsletter v7_02 3/24/2004

and cables, connectors, EMC

and crosstalk

Reason for Ground Split There are indeed applications so sensitive that they require separation of the analog and digital ground regions. Newsletter v9_04 3/24/2006

and crosstalk, reference plane

Noise Isolation Achieving isolation greater than 80 dB. Newsletter v2-13 5/19/1998

and EMC

Moats and Floats How to conduct multiple comparative layout studies in one pcb fabrication cycle. ED 2/17/1997

Picket Fences (by W. Michael King) About the use of a "picket fence" array of ground vias to shield internal sections of a board from each other. Newsletter v2-16 6/8/1998

Radiated Digital Ground Noise Ideally, you should ground your digital logic, the chassis, any cable grounds, and the cable shield (if present) to a common point. Newsletter v2-17 6/26/1998

and EMC, power system

Front-Connected Power Supply Why connections on the front side of a plug-in card are a bad idea. Newsletter v4-17 12/5/2001

and EMC, reference plane

Ground Fill Isolated, discontinuous regions of ground fill do not help reduce magnetic-field coupling between traces or radiation from the board. EDN 5/26/2005

and layer stack, power system

Ground/Power Planes At very high speeds, bypass capacitance needs to be within less than 1/10 of a rising-edge-length in order to function effectively. Newsletter v1-8 8/15/1997

and probes

Mysterious Ground All good probes come with short, tiny ground attachments. For single-ended measurements, don't depend on mysterious ground connections. Always use a good, short ground connection. EDN 2/7/2002

high-speed digital design

Ground Bounce Calculations On page 62 of the High-Speed Digital Design Text… where does the factor of 1.52 come from? Newsletter v1-12 9/26/1997

Equivalent Circuit Source Impedance What is the true source impedance of the equivalent circuit at figure 1.6 (page 13)? Newsletter v2-9 3/23/1998

and crosstalk, proximity effect, return current

Proximity Effect III Justification for crosstalk approximation (see High-Speed Digital Design p. 190, eqn. [5.1]) Newsletter v4-8 10/3/2001

and EM fields, return current, via

Via Inductance The inductance of a via depends on the path of returning signal current. Newsletter v6-04 3/15/2003

and power system

Resistance Regarding page 414, equation for calculating the DC resistance of power planes based on the diameters of two contact points space at X amount of distance. Newsletter v1-11 9/15/1997

hot plugging,

and power system

Hot Plugging and Beefy Guys Named Mark Mark McGwire reminds me of some of the technicians I have seen working on large systems EDN 11/5/1998

interconnections,

Interconnections Matter When you look at a digital machine, if you are not looking at the interconnections, you are missing one of the most important parts of the structure. EDN 5/13/1999

and clocks, level translation

When to use AC Coupling When should one adopt DC coupling versus AC coupling? Newsletter v4_15 11/13/2001

and multi level

(The) Future of On-Chip Interconnections Today's chip-layout software takes into account the RC propagation delays of major bus structures and clock lines. In tomorrow's designs, at even higher speeds, the full RLC nature of the on-chip transmission channels will emerge. EDN 2/3/2000

and system-on-a-chip

Second-Level Interconnects A reader suggests, "The days of discrete design and interconnect are rapidly disappearing, if not gone already." Newsletter v2-15 6/4/1998

jitter,

Jitter Measurement What is the best way to measure Signal jitter using a Digital Oscilloscope? Newsletter v3-22 10/21/1999

and characteristic impedance, crosstalk

Memory Bus Crosstalk I am currently working on high speed memory bus with “interconnect jitter”. My memory recommends changing the bus geometry to improve timing. Newsletter v9_06 8/22/2006

and clocks

Jitter and Phase Noise Converting spectral-power-density noise measurements into rms and peak-to-peak jitter. Newsletter v4-7 6/25/2001

Clock Jitter Propagation Any sort of resonance, even a tiny one, spells disaster for a highly cascaded system. EDN 2/6/2003

Jitter and SNR Combined I would rather not consider of the joint probability of occurrence of vertical noise and horizontal jitter in the same equation. Newsletter v7_06 11/18/2004

and clocks, EMC

Signal Integrity Mailbag My recent column on intentional clock modulation (EDN, Aug 3, 1998, pg 24) spurred some interesting responses from readers. EDN 10/8/1998

Jitter-Free Clocks Is there any way to make a timing reference that has low jitter and low spectral peaks and at the same time is compatible with zero-delay-repeater structures? EDN 8/5/1999

and simulation, testing

Eye Don't Like It An eye diagram makes a wonderful way to check finished system margins, but a terrible diagnostic tool. EDN 11/9/2006

layer stack,

and back plane, differential signaling, serial link

Backplane Design Differential trace geometry, power and ground stackup for big backplane. EDN 5/25/2000

and connectors, crosstalk, via

Connecting Layers In a multi-layer pcb the vias perform the role of a tiny connector, where the signal-to-ground-via ratio controls via crosstalk. EDN 7/22/2004

and differential signaling, layout, skew

Asymmetry in Broadside Configuration In general I avoid broadside-coupled traces unless they are made necessary by routing considerations. EDN 11/14/2002

and grounding, power system

Ground/Power Planes At very high speeds, bypass capacitance needs to be within less than 1/10 of a rising-edge-length in order to function effectively. Newsletter v1-8 8/15/1997

and power system, return current

Interplane Capacitance Follow-up to "High-Speed Return Signals" newsletter v1-15, discusses the effective useful radius of the interplane capacitance. Newsletter v3-21 8/30/1999

and reference plane

Dual Ground Shields Theoretically, if the planes are completely solid (no holes), they would act as near-perfect isolation boundaries, BUT you have to consider the holes… Newsletter v3-19 8/12/1999

and return current

High-Speed Return Signals How do high speed return signals travel on a 4 layer pc board? Newsletter v1-15 10/27/1997

Ten Layer Stack Discussion of multi-layer board stack for system with multiple power voltages. Newsletter v2-11 4/27/1998

Ground Current Details the exact path of returning signal current when a chip switches HI or LO Newsletter v3-7 3/15/1999

layout,

and bypass capacitors

Operating Above Resonance It's OK to use a bypass capacitor well above its point of series-resonance. That's the normal mode of operation for most bypass capacitors. ED 4/14/1997

Bypass Arrays Does anyone out there actually DESIGN their bypassing networks? Newsletter v1-6 7/25/1997

Capacitor Placement The function of a bypass capacitor is this: to help returning signal current get from the board back into the driver. Newsletter v2-1 1/7/1998

Bypass Capacitor Layout Little traces between your bypass capacitors and the power planes have a big effect on performance. Newsletter v2-3 1/23/1998

(The) Way Home Current always makes a loop. If it goes out, it must find a way back home. The shapes of both the outgoing and the return paths affect the observed inductance. EDN 6/22/2000

Parasitic Inductance of Bypass Capacitors You can estimate the parasitic series inductance of a bypass capacitor in a multi-layer board with solid power and ground planes. EDN 7/20/2000

and bypass capacitors, power system

Capacitor Layout Matters Your problem is likely caused by the layout, which has more than tripled the inductance of each bypass capacitor, not the values of types of capacitance. EDN 9/5/2002

and cables, reflections, termination

Matching Pads The only passive circuits that guarantee good impedance translation for wideband signals are resistive pads. EDN 12/21/2000

and crosstalk

Trace Between Capacitors Will crosstalk occur if I route a trace underneath a bypass capacitor? Newsletter v3-4 1/28/1999

Crosstalk at Right Angles Crosstalk for traces crossing at right angles. Newsletter v3-6 2/26/1999

and crosstalk, differential signaling

Mitigating Crosstalk What can be done to reduce the amount of crosstalk in a pcb. Newsletter v6-01 1/20/2003

and data coding, reflections

AC Coupling Layout (for XAUI 3.125 Gb/s) The parasitic body capacitance of the AC coupling caps perturbs the characteristic impedance of your transmission line. Newsletter v10_02 5/18/2007

and differential signaling

Differential Routing Is it better to route differential traces over/under (broadside) or side-by-side (edge-coupled)? Newsletter v2- 30 11/11/1998

and differential signaling, layer stack, skew

Asymmetry in Broadside Configuration In general I avoid broadside-coupled traces unless they are made necessary by routing considerations. EDN 11/14/2002

and multi drop

Four-Way Distribution How to best distribute a bus to four different loads. Newsletter v1-14 10/17/1997

Tricky DRAM Lines The app note I'm looking at suggests that my DRAM address lines run in a "T" shape… with a ground plane cut under the DRAMs Newsletter v1-20 12/15/1997

To Tee or Not To Tee? The basic problem with this topology is that all three branches are long compared to the length of a rising edge. EDN 2/2/1998

and multi drop, power dissipation

Three Drop Bus The three privileged locations on a long net are at one end, the other end, and right smack in the middle. Newsletter v4-12 10/18/2001

and multi drop, ringing

Driving Two Loads Any time you build a split-tee, always simulate the circuit with a maximal degree of capacitive imbalance in the receivers. EDN 7/19/2001

and multi drop, rise time

Dual Transceivers You can make extremely small, zero-cost, high-performance switches from ordinary solder pads and solder paste. EDN 6/10/1999

and multi drop, termination

Really Cool Bus This unidirectional structure supports one driver with many, many loads. EDN 10/26/2000

Hairball Nets Terminating big globs of unstructured loads. Newsletter v4-10 10/8/2001

and probes, skew

Tiny Difference Measuring a tiny time difference like 5 ps can be quite challenging. Anjaly will need well-matched, skew- calibrated probes and perfectly symmetric attachments to the board. Newsletter v9_08 12/21/2006

and reflections, stripline

Breaking Up a Pair The two traces comprising a differential pair, when routed close together, share a certain amount of cross- coupling. This coupling lowers the differential impedance between the traces. EDN 11/9/2000

and termination

Placement of End Termination The sequencing of the end-terminator and its associated load can make a measurable difference in signal quality. Newsletter v2-7 2/25/1998

How Close is Close Enough? How close to the driver must you keep your series terminations? EDN 4/9/1998

level translation,

ECL and PECL Can I directly connect a differential ECL signal to a differential PECL device? Newsletter v2-22 8/25/1998

ECL and PECL Reader Responses Further discussion of ECL-to-PECL level translation. Newsletter v2-23 9/1/1998

and clocks, interconnections

When to use AC Coupling When should one adopt DC coupling versus AC coupling? Newsletter v4_15 11/13/2001

and data coding

and data coding, reflections, serial link

DC Blocking Capacitor Placement Slower systems sometimes benefit from placing the DC blocking capacitors close to the source, but not multi-gigabit systems. Newsletter v7_08 12/12/2004

DC Blocking Capacitor Value How do I choose the value for a DC blocking capacitor in a serial link application? Newsletter v7_09 1/10/2005

and ground bounce, rise time

Asymmetric Noise Margins Extreme asymmetries in the noise margin budget for a logic family create a preferred logic level. EDN 3/15/2001

and termination

Yao! What a Handshake Making the output voltage equal VT is the easiest thing in the world for a driver. The terminating voltage is a "natural resting place". If you disconnect the driver, the load immediately relaxes, all by itself, to VT. EDN 2/7/2008

Z[min] Understanding Z[min], dear reader, is the secret to successful end-termination design. EDN 2/27/2008

management,

Signal Integrity Broadcast Pep talk to management about the importance of signal integrity. Web audio

Keeping Up With Moore multi-layer pc-boards, solid power and ground planes, surface-mount technology, reflow soldering, and the BGA package were the prominent advances in packaging during the last 20 years. EDN 5/7/1998

Building a Signal Integrity Department What sort of a mission do you give to a department of signal integrity? EDN 6/4/1998

Managing Scotty Scotty to Kirk, "We cannot get the shields back in less than an hour, Captain. The Klingon attack cracked our DiLithium crystal, and there's antimatter leaking everywhere…" EDN 6/7/2001

Why Johnny Can't Design a High-Speed Digital System As a class, digital engineers are less well equipped now than they were 30 years ago to design a high- speed digital system. DesignCon 2003 2/17/2003

When Everything Matters Squeeze that last drop of performance from a CMOS architecture by turning up the clock or adding a few new features and you may choke on the curse of complexity—where every decision you make interacts with every other decision. EDN 1/6/2005

Specsmanship Every Joe at the lumberyard understands that a 2x4 does not measure two inches by four inches. EDN 2/2/2006

Why Teach Science? Science is not for everybody. You could live like an aborignal, running around naked in the forest chasing deer with bows and arrows, for all I care. EDN 2/1/2007

Rollback RoHS Lead-free solder is not a "green" solution. Lead-free solder actually damages the environment more than 60/40 solder. Newsletter v10_01 4/16/2007

Aunt Judy Old Aunt Judy approaches you at a reception, with a little halt in her voice, and says, "You know about electronics, right? Well, I've got this old 8-track tape player… EDN 11/8/2007

and attenuation, serial link

and bypass capacitors, power system

ESR of Regulator Output Capacitor How can the ESR of a bulk capacitor (tantalum or electrolytic capacitor) affect a linear voltage regulator? Newsletter v5-3 2/25/2002

and crosstalk, testing

Margin Testing (by JP Miller) Testing a link in isolation is never sufficient; links must be tested in combination with other noise sources. EDN 3/3/2005

and electromigration, power dissipation

and EMC

Not all EMC engineers are bald If you want to keep doing what you love to do you must constantly re-educate yourself. EDN 1/24/2002

and Ernie

Ernie's Story Engineers without a basic understanding of high-speed effects will likely end up just like Ernie, sitting in somebody else's office, fidgeting and sweating. ED 12/1/1996

and power system, transmission line

Big Hurl Engineers enjoy a long tradition of experience with dynamic processes. We have developed over the centuries many diverse means of dealing with them. EDN 7/21/2005

and probes

Approaching the Edge Worst-case budgets don’t work if you don't include all the necessary factors, or if you make wrong assumptions to fill in gaps in the available data. DesignCon 2004 2/1/2004

and testing

Practical Advice Years ago, an engineer named Allen Goodrich gave me a unique piece of advice. EDN 11/22/2001

Words of Wisdom What instructions would you give to a development team working on a 10 Gb/s serial link? EDN 4/3/2003

Diagnostic Testing (and Tasting) Diagnostic testing requires a keen awareness of all aspects of the system at hand. The operator must remain ever vigilant during testing, aware of even the tiniest clue about system behavior. EDN 4/26/2007

metastability,

Metastability in Flip Flops What happens if you have two flip-flops in series, both using the same clock, and the first one goes metastable? Newsletter v3-15 7/14/1999

Acceptable Failure Without clearly quantified limits on the "acceptable probability of failure," you never know whether you have implemented too little or too much of your favorite failure-rate cure. EDN 3/2/2000

Metastable Persons When you violate the setup-and-hold times on a flip-flop, the output might erratically go high, stay low, or pop one way and then back again. EDN 3/16/2000

Flip-Flops What actually causes the metastability in Flip- Flops? Newsletter v4-2 5/12/2000

and skew

Inducing Metastability What if I *WANT* to induce the metastable state in a flip-flop? Newsletter v4-4 6/4/2001

microstrip,

and attenuation, skin effect

Passivation and Solder Mask Copper traces on outer layers must be protected from corrosion by passivation or by coating them with an inert material. EDN 6/13/2002

and dispersion, transmission line

Strange Microstrip Mailbag Follow-up to April 26, 2001 column in EDN, “Strange Microstrip Modes. Newsletter v4-16 11/28/2001

and probes

Scrape It I only know six ways to remove solder mask for probing: Scraping, milling, grinding, micro-blasting, chemical stripping, and ultraviolet (UV) illumination. EDN 5/1/2008

and reflections, transmission line

Who's Afraid of the Big, Bad Bend? Right-angle bends in PC-board traces perform perfectly well in digital designs in speeds as fast as 2 Gbps. EDN 5/11/2000

multi drop,

and back plane, ringing

Bus Architecture and Timing The ratio (bus delay)/(clock period) is a key indicator of bus design difficulty. DesignCon 1999 1/30/1999

and delay, PCI

and layout

Four-Way Distribution How to best distribute a bus to four different loads. Newsletter v1-14 10/17/1997

Tricky DRAM Lines The app note I'm looking at suggests that my DRAM address lines run in a "T" shape… with a ground plane cut under the DRAMs Newsletter v1-20 12/15/1997

To Tee or Not To Tee? The basic problem with this topology is that all three branches are long compared to the length of a rising edge. EDN 2/2/1998

and layout, power dissipation

Three Drop Bus The three privileged locations on a long net are at one end, the other end, and right smack in the middle. Newsletter v4-12 10/18/2001

and layout, ringing

Driving Two Loads Any time you build a split-tee, always simulate the circuit with a maximal degree of capacitive imbalance in the receivers. EDN 7/19/2001

and layout, rise time

Dual Transceivers You can make extremely small, zero-cost, high-performance switches from ordinary solder pads and solder paste. EDN 6/10/1999

and layout, termination

Really Cool Bus This unidirectional structure supports one driver with many, many loads. EDN 10/26/2000

Hairball Nets Terminating big globs of unstructured loads. Newsletter v4-10 10/8/2001

and PCI

Bi-directional Alternatives Hanging four loads on a bi-directional line; how PCI "reflected wave switching" works Newsletter v3-3 1/22/1999

and termination

Bi-directional Terminations Using a series terminator at both ends of the line. Newsletter v2-20 8/6/1998

multi level,

and back plane, serial link

and bandwidth, serial link

(The) Torches and the Hair Mankind has a long history of experience dealing with bandwidth-limited communication channels. DesignCon 2003 2/17/2003

and connectors, crosstalk

Shannon Says Connector vendors will soon realize that great improvements in the information-carrying capacity of their products may be had by reducing crosstalk. EDN 11/13/2003

and interconnections

open drain,

and termination

Open-Drain Lines Should I use one pull-up resistor located somewhere in the middle of my line, or two resistors of twice the value located at each end? Newsletter v2-5 2/9/1998

overshoot,

and bandwidth, TEM mode, transmission line

Strange Microstrip Modes "Quasistatic" values of capacitance and inductance are the values you get at low frequencies, near dc. EDN 4/26/2001

and clocks, skew

and electromigration, ESD, ringing

(For Your) Protection Protection diodes have a limited lifetime—don't wear them out. EDN 12/9/2004

and ringing

Severe Overshoot Will overshoot and undershoot impact the receiver, damage it or cause excessive recovery time? Newsletter v2-31 12/2/1998

Severe Overshoot Mailbag ...the clamp diodes shot current into the VCC net… …make sure you are measuring the overshoot correctly… ...Undershoot on some lines on some SRAM chips will cause "weak writes"… Newsletter v3-1 1/14/1999

PCI,

PCI Bus Discussion of "second-reflected-wave switching" and terminations. Newsletter v2-28 10/22/1998

and delay, multi drop

and multi drop

Bi-directional Alternatives Hanging four loads on a bi-directional line; how PCI "reflected wave switching" works Newsletter v3-3 1/22/1999

power dissipation,

and electromigration, management

Relevance of Physics The engineering curriculum for first-year s