On Chip Bypassing with Series Terminations
Figure 1 depicts a simple totem-pole I/O circuit driving a perfect, series-terminated transmission line. Assume in your analysis that optional capacitor C1 is not connected and that the line begins at rest with zero voltage and current everywhere.
At time t1, close switch A. Current flows from pc-board VCC through the package inductance, LV. It traverses switch A, the series-terminating resistor, and enters the transmission line. This action conveys a half-sized rising edge down the structure. The output current associated with this initial action has magnitude (1/2)(VCC/Z0). The current persists for one full round-trip time on the net, ending at time t2, after which the net requires no additional current to hold the line in its fully charged state.
As current surges through the package inductance, LV, it causes on-chip voltage perturbations at node V1, as Figure 1 shows.
At time t3, you open switch A. This event by itself causes no transient effects, because no current was flowing through the switch immediately before opening it. At the same time, you close switch B, sinking a pulse of current through switch B and inductor LG to ground and causing ground-bounce perturbations at node G1, as Figure 1 again shows.
Adding the on-chip bypass capacitance, C1, between nodes V1 and G1 forces the transient voltages at those two points to be the same. The circuit then averages the waveforms V1 and G1 in Figure 1. Doing so produces equal-sized glitches on both V1 and G1 at every transition, but with half the previous magnitude.
The capacitor diverts the transient currents, sending half through the power pins and half through the ground pins on each excursion. The die now fully uses all of its power and ground pins on every switching event instead of using only the power pins when going high and the ground pins when going low. In this series-termination-with-on-chip-bypassing architecture, you can skirt by with fewer total power and ground pins than would have been possible without the on-chip bypass capacitor.
Now take the bypass capacitor away and double up the driver to create a differential pair, still using series terminations. The differential architecture ensures that a low-side switching event, such as t3 and t4, simultaneously accompanies each high-side switching glitch (at t1 and t2). This differential-series-terminated architecture guarantees that the noise perturbations at V1 and G1 always move in opposition to each other. An on-chip bypass capacitor applied to this situation performs brilliantly. If of sufficient size, it almost completely eliminates transient voltages on both rails. Any die that uses differential signaling with series-terminated lines benefits noticeably from on-chip bypass capacitance.
Bypass capacitors connected at the package level (within a BGA package but outside the die) reduce that portion of the power-system noise attributable to the inductance of the power and ground connections within the BGA substrate. However, they do not reduce the noise attributable to wire-bond wires (if present) or the on-chip distribution.
My next column considers the effectiveness of on-chip capacitance for end-terminated applications: On-Chip Bypassing with End Terminations.