Short-Term Impedance of Planes
It's a gorgeous day here in the Methow Valley region of Washington state. The snow is nearly all melted and the grass is turning a healthy green color. I hope you have enjoyed a pleasant winter season.
The last newsletter left open a basic question about the efficacy of parallel planes at extremely high speeds, a question which I hope to fully answer in this issue.
Short-Term Impedance of Planes
By Dr. Howard Johnson
The last newsletter prompted a basic question about the efficacy of parallel planes.
In a four-layer board, assume you have a trace that jumps through a via from layer 1 to layer 4. Before the via, the trace lies adjacent to plane 2. After the jump, the trace lies adjacent to a different plane, layer 3.
This configuration is illustrated in Figure 1 (copied from newsletter v6-04, "Via Inductance"). The figure shows how at every point where high-frequency signal current flows, an equal and opposite current flows on the solid reference plane adjacent to the signal conductor. The principle of equal and opposite current on the plane implies that, somewhere near the signal via, the returning signal current associated with this trace must hop between layers 2 and 3.
Figure 1—Near the via, returning signal current originating on layer 2 must somehow leap to layer 3 ("High-Speed Signal Propagation", Fig. 5.33, p. 353)
Doesn't the returning signal current just pop between the planes through the parasitic capacitance of the planes themselves, you might ask?
The short answer is that in typical cases where the planes are widely spaced (as in a stripline cavity) the current seeks out the nearest metallic connection, such as a via or bypass capacitor, and follows that path.
To investigate that question I have set up a simulation that calculates the impedance between two parallel planes, as measured at the location the signal via in Figure 1. To keep the math simple, I will assume the planes are circular (as opposed to the square geometry shown in the figure).
I will try various plane radiuses including 1, 2, 3, 5, and 8 cm. The inter-plane separation in each case will be h = 0.030 in. (0.76 mm), filled with a material having a dielectric constant of 4.3, corresponding to the situation normally used when implementing a very thick board with striplines between the planes.
In microwave parlance, the "coupling port" that gives access to the cavity between the planes is the via clearance hole, which has an assumed radius of rc = 0.010 in. (0.25 mm).
The simulation pumps a 20-mA step of current from one plane to the other at the clearance hole location. The size of this step corresponds to the jolt of current that would prevail when sending a 1-V p-p signal from a 50-ohm trace through the signal via. The 10-90% signal risetime is tr = 100 ps (pretty fast).
If you have a calculator handy, you should check the length of this rising edge as it slides down the transmission structure, as measured from its 10% to its 90% values. The length is calculated as the signal rise or fall time tr times c, the speed of light, all divided by the square root of Er the dielectric constant of the material between the planes. Your answer should come out to 0.57 in. (1.4 cm). Half a risetime corresponds to 0.7 cm. Hold onto that bit of data; we will need it in a moment.
To set up this experiment I first broke the planes into a set of concentric rings. The thickness (in the radial direction) of each ring was 0.04 cm (about 1/35th of the length of the rising edge). The number of rings required to model a disk of radius 8 cm was 200.
Extra for experts
The technical setup for this experiment is best comprehended by first cutting the whole arrangement into eight wedges (like a pie). A 1/8th slice of the pie forms a horn-shaped transmission line, broken into chunks at radial increments of 0.04 cm. Each little chunk acts like a short, fat segment of transmission line. As you proceed out from the center, the chunks get wider and wider, which means the characteristic impedance of each chunk must be getting progressively smaller.
The experiment calculates the effective impedance and length of each of the little chunks and then concatenates all 200 of these chunks together into one big cascade of two-port models. I used MathCad to compute the input impedance of this whole structure. By symmetry, I then take the impedance of this one single pie slice and divide it by eight to obtain the impedance of the whole pie.
I checked my solution against the standard Bessel-function solution for the impedance of a circular plate and it matched perfectly for the case of no losses within the planes. Then I modified the MathCad model to incorporated both skin effect and dielectric losses using the approach outlined in High-Speed Signal Propagation. The losses substantially damp resonances in the frequency response.
Back now to our regular program...
Figure 2illustrates the impedance of the various-sized disks used in this experiment (all having a dielectric thickness of 0.030 in.). At frequencies below 100 MHz, all five disks exhibit a clearly capacitive behavior (impedance trending down with increasing frequency). The total capacitances of the disks, listed in order of decreasing size, is 1005, 392, 141, 63, and 16 pF.
Figure 2--Below the first series resonance, the impedance depends on the total capacitance of the planes. Above the first series resonance, the impedance trends generally up on a slope corresponding to an inductance of (in this case) approximately 1 nH.
Somewhere above 100 MHz, depending on the size of the disk, the impedance reaches its nadir and begins to climb. This minimum-impedance point is called a point of series resonance. The resonance has to do with the speed of round-trip wave propagation back and forth from side to side (or center to edge, depending on how you look at it) across the disk. The bigger disks have a lower point of series resonance.
Above the point of first series resonance, the impedance trends generally upward amongst a multitude of horrid resonances. Figure 2 shows a black line corresponding to the impedance of a 1-nH inductor. Notice that, regardless of the size of the disk, all the curves trend upward in a pattern reminiscent of the 1-nH inductance.
In this example, you may model the region surrounding the first series resonance as simply a capacitor equal to the total capacitance of the disk placed in series with an effective series inductance of 1 nH. If you can "see through" the gyrations induced by the upper-level resonances this simple L-C series model serves pretty well at all frequencies.
I should like to thank Minjia Zu, Yun Ji, Todd Hubing, Thomas P. Van Doren, and James L. Drewniak for making clear the theoretical basis for the existence of this effective series inductance in their paper titled, "Development of a Closed=Form Expression for the Input Impedance of Power-Ground Plane Structures", published in the proceeding of the IEEE EMC Symposium 2001.
Figure 3 shows the step-response waveforms corresponding to the six impedance plots in Figure 2. Amazingly, the response is the same during the rising edge in each case, regardless of the size of the disk. This happens because the outer reaches of the disk (more than 1/2 of a rise-time from the center) are located too far away to possibly influence the signal before the conclusion of the rising edge. In order the influence the response during the initial risetime, an object must be located close enough that electromagnetic energy can propagate to the object, interact with it, and return, before the risetime is complete. From this constraint derives the idea that no areas of the disk further away than 1/2 of a risetime can possible influence the initial response.
Your earlier calculation showed that half a risetime corresponds to 0.7 cm. Since all the disks have a radius at least that big, you should expect no difference in the initial response in each case. Additional plane material located further away than 0.7 cm simply doesn't make any difference on a scale of time as small as 100 ps. All that matters during the initial rising edge is the effective inductance of the disk, which is the same in each case. In this example with the planes separated by 0.030 in., Er=4.3, and the access port radius equal to 0.010 in. the effective inductance is roughly 1 nH.
Figure 3--During the first rising edge, the response depends only on the effective inductance of the planes.
Reflections from the edge of the disk arrive at successively later intervals in the larger disks. After the initial response, the each disk begins to charge up on a ramp slope corresponding to the amount of that disk's total capacitance.
The impact of the plane's effective inductance on your signals is precisely the same as if you had connected an inductance of that size in series with your trace. A single-ended signal traversing an inter-plane cavity of height 0.030 in. through a clearance hole of 0.010-in. radius will therefore generate a short reflected pulse whose amplitude, as a fraction of the incoming step height, equals (1/2)(L/Z0)(1/tr), where L is the effective inductance, Z0 the characteristic impedance of the line, and tr the signal risetime. Plugging in 1 nH, 50 ohms, and 100 ps gives a reflected pulse height of 10% of the incoming step amplitude. At a risetime of 1 ns (1000 ps) you get only a 1% reflection, which is why we digital designers have not worried about this effect up until now. When you get down to sub-nanosecond risetimes, however, it really starts to matter.
The last (lowest) plot in Figure 2 shows the step response of a 1 nH inductance. This is the effective inductance you would get if you connect the planes together with a single via having a hole radius of 0.005 in. (0.010-in. diameter), separated 0.140 in. from the signal via. During the first rising edge a via of this configuration presents the same impedance as the planes, so it takes half the current. This reduces the magnitude of the reflected signal by a factor of two as well reducing both EMI and crosstalk.
That brings me back to the subject of this article, which has to do with the flow of returning signal current in a multi-layer board. If you interconnect the planes with vias or low-inductance bypass capacitors, a substantial fraction of the returning signal current flows through your intentional interconnections.
As you scale down the height h between the planes the impedance of the planes shrinks in direct proportion to h. This scaling principle is enormously helpful. It is the reason I like to see your power and ground planes as close together as possible. If you get the planes close enough (for example a power and ground pair with 2-mil height), the impedance of the planes themselves can become sufficiently low that you do not need additional interconnections to help your return current pop from one plane to the other. On the other hand, when your signals traverse a relatively tall stripline cavity, additional interconnection vias play an important role in containing signal reflections, crosstalk, and EMI.
Best Regards,
Dr. Howard Johnson