Dr. Howard Johnson last public seminar

DC Blocking Capacitors

High-Speed Digital Design Online Newsletter: Vol. 7 Issue 08

I'd like to thank Ray Anderson, founder of the si-list, for his kind words about our new RocketIO movie. In case you didn't see his announcement, here's some excerpts from what Ray had to say:

"…a new SI tutorial (provided on two DVD's) produced by Dr. Howard Johnson for Xilinx is now available for purchase by the general public. It addresses high-speed signal integrity techniques and loss budgeting (with a slant towards Xilinx RocketIO devices) in an easy to understand format. It includes detailed technical discussions along with 'in-the-lab' demonstrations of the concepts.

"The 1.5 hour tutorial is available from the Xilinx online store for about $20.  The actual URL is horrendously long, but you can get there by going to http://www.xilinx.com then clicking on the 'Online Store' link and then the 'DVD Tutorials' link under the 'Design Resources' category.

"…I was impressed with the presentation and thought others might be as well."

The tutorial addresses topics of interest to anyone implementing high-speed multi-gigabit serial links, whether using the RocketIO transceivers or not.

DC Blocking Capacitors

Jaime Melanson, of Dell Enterprise Server Design writes:

Hi Dr. Johnson, I always thoroughly enjoy reading your newsletters. You do an excellent job of explaining difficult concepts so that even an engineer recently out of college (as I am) can understand and apply the lesson. I have never had the need to ask my own question before, but a design question has recently come up in my work that I think you may be able to help with.

We are using DC blocking caps in the design of high-speed differential serial pairs that run about 20" through board and connectors (no cables). The caps are meant to be grouped with the transmitter, but there is not a clear requirement to place them right near the transmitter.

My questions are:

  1. Does the placement of the caps matter? What kinds of effects occur when the caps are moved farther away?
  2. How do you choose the cap values?

Thanks!

Thanks for your interest in High-Speed Digital Design.

Regarding your inquiry, a good introduction to the subject of DC blocking capacitors appears in my article "When to use AC Coupling". I will assume your familiarity with that article.

To begin our discussion, let me state clearly that the phrase "AC coupling capacitor", and "DC blocking capacitor" refer, in my system of terminology, to the same thing. Any capacitor placed in series with your signal flow tends to pass the high-frequency (AC) portions of your signal while simultaneously blocking the low-frequency (DC) portions.

Your question about the location of the DC blocking capacitor involves the reflections generated on your transmission structure due to the presence of that capacitor. To understand the reflection issue you must become aware of two distinct capacitances we will discuss. First, there is the normal, lumped-element capacitance of the DC blocking capacitor. This amount, some hundreds of nanofarads, acts in series with your signal. I shall call this the series capacitance.

Second, there is the parasitic capacitance created by the body of the DC blocking capacitor in proximity to the reference plane. This amount is much smaller, perhaps only a few picofarads. I shall call this the body capacitance.

Keep in mind that the capacitor is physically much larger than the PCB trace to which it is attached. Assuming the whole structure (transmission line plus capacitor) is implemented in planar fashion at a constant height above the nearest reference plane, the disproportionate size of the capacitor virtually guarantees that its body capacitance will create, in the local vicinity, an area of impedance less than the nominal Z0 of the bare transmission line. Regions of low impedance create negative reflections; therefore, we may expect that the body capacitance will create, in response to an incoming positive step, a negative reflection passing back towards the source.

As with any reflection, if it occurs within much less than 1/2 a baud interval of either the source or the load, the reflections generated by each data edge will generally fall somewhere within that self-same baud interval. On the other hand, reflections generated at points more remote from either source of load create interference patterns that persist into subsequent bits (i.e., intersymbol interference). This principle motivates the idea that DC blocking capacitors should be installed close to the transmitter.

For example, a 10-BASE T system, operating at 10 Mb/s, has baud intervals of 100 ns. Placing a DC blocking component within one foot of the source (4 ns round-trip in FR-4) easily satisfies the no-ISI requirement.

A 10 Gb/s system behaves quite differently. In that system each bit, as it slides down your transmission medium, occupies a space only a half an inch long (100 ps). At that speed, the phrase "much less than 1/2 a baud interval" implies a distance of probably less than one tenth of an inch, an impracticably small spacing.

You may conclude from this discussion that slower systems sometimes benefit from placing the DC blocking capacitors close to the source (or, by reciprocity, close to the load).

In very high-speed systems you cannot practically obtain that same benefit. What you must do instead is lay out the blocking capacitor in such as way that it has no observable impact on the signals conveyed. In many cases, the DC blocking capacitor must have a hole cleared in the reference plane underneath the component to relieve the excessive capacitance underneath the body of the component. All other traces must be kept clear of this region.

The choice of whether to place the capacitor near the source or load end of the transmission system depends mostly on mechanical convenience, except for one issue having to do with removable interfaces. If your transceiver can be unplugged, especially if it is hot-plugged, a DC blocking capacitor mounted on the pcb with the transmitter serves to limit the maximum DC current that can be drawn from the transmitter in the event the interface pins are inadvertently shorted to ground, or some other power voltage, during the process of insertion. Particularly for families of digital logic that easily blown out by short-circuiting them to ground this feature can be quite useful. Receivers generally suffer any voltage within the power rails without damage, although there can be exceptions especially in a hot-plugging environment if the card being inserted is not powered up at the time the inputs are connected to a source of live transmitted signals—this case argues for associating your DC blocking capacitors with the receiver.

I have some words of advice for you about your second question that shall have to wait until I have time to pen another newsletter.

Speaking of new topics, I've just begun planning a brand-new seminar, and would appreciate any suggestions you may have about its contents, or any changes or updates you would like to see incorporated into my existing courses. I appreciate the thousands of readers who write each year requesting information, or bringing up interesting topics for this newsletter, and encourage you to keep in touch.

Best Regards,
Dr. Howard Johnson